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80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet product features code compatible with all 80960jx processors high-performance embedded architecture ? one instruction/clock execution ? core clock rate is: 1x the bus clock for 80960ja/jf/js 2x the bus clock for 80960jd/jc 3x the bus clock for 80960jt ? load/store programming model ? sixteen 32-bit global registers ? sixteen 32-bit local registers (8 sets) ? nine addressing modes ? user/supervisor protection model two-way set associative instruction cache ? 80960ja - 2 kbyte ? 80960jf/jd - 4 kbyte ? 80960js/jc/jt - 16 kbyte ? programmable cache-locking mechanism direct mapped data cache ? 80960ja - 1 kbyte ? 80960jf/jd - 2 kbyte ? 80960js/jc/jt - 4 kbyte ? write through operation on-chip stack frame cache ? seven register sets may be saved ? automatic allocation on call/return ? 0-7 frames reserved for high-priority interrupts on-chip data ram ? 1 kbyte critical variable storage ? single-cycle access 3.3 v supply voltage ? 5 v tolerant inputs ? ttl compatible outputs high bandwidth burst bus ? 32-bit multiplexed address/data ? programmable memory configuration ? selectable 8-, 16-, 32-bit bus widths ? supports unaligned accesses ? big or little endian byte ordering high-speed interrupt controller ? 31 programmable priorities ? eight maskable pins plus nmi# ? up to 240 vectors in expanded mode two on-chip timers ? independent 32-bit counting ? clock prescaling by 1, 2, 4 or 8 ? internal interrupt sources halt mode for low power ieee 1149.1 (jtag) boundary scan compatibility packages ? 132-lead pin grid array (pga) ? 132-lead plastic quad flat pack (pqfp) ? 196-ball mini plastic ball grid array (mpbga) order number: 273159-00 6 august 2004
2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel?s website at http://www.intel.com. alertview, anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct connect, ct media, dialogic, dm3, ethere xpress, etox, flashfile, i386, i486, i960, icomp, instantip, intel, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, intel sx2, intel create & share, intel gigablade, intel inbusiness, intel inside, intel inside logo, intel netburst, intel netmerge, intel netstructure, intel p lay, intel play logo, intel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, intel xscale, iplink, itanium, landesk, lanrov er, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, remoteexpress, shiva, smartdie, solutions960, sound mark, storageexpress, the computer inside., the journey inside, tokenexpress, trillium, voicebrick, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsi diaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? intel corporation, 2002 , 2004
datasheet 3 contents contents 1.0 introduction ............................................................................................................................... ..... 7 2.0 80960jx overview .......................................................................................................................... 9 2.1 80960 processor core........................................................................................................ 10 2.2 burst bus ................................................................................................................... .........11 2.3 timer unit .................................................................................................................. .........11 2.4 priority interrupt controller............................................................................................... ...11 2.5 instruction set summary ....................................................................................................1 2 2.6 faults and debugging........................................................................................................ .12 2.7 low power operation ......................................................................................................... 12 2.8 test features............................................................................................................... .......12 2.9 memory-mapped control registers ....................................................................................13 2.10 data types and memory addressing modes......................................................................13 3.0 packaging information ................................................................................................................15 3.1 available processors and packages ..................................................................................15 3.2 pin descriptions ............................................................................................................ ......16 3.2.1 functional pin definitions ......................................................................................16 3.2.2 80960jx 132-lead pga pinout .............................................................................23 3.2.3 80960jx 132-lead pqfp pinout ...........................................................................27 3.2.4 80960jx 196-ball mpbga pinout ..........................................................................30 4.0 electrical specifications .............................................................................................................35 4.1 absolute maximum ratings ................................................................................................35 4.2 operating conditions ........................................................................................................ ..35 4.3 connection recommendations...........................................................................................36 4.4 vcc5 pin requirements (vdiff) .......................................................................................36 4.5 vccpll pin requirements ................................................................................................37 4.6 d.c. specifications ......................................................................................................... ....38 4.7 a.c. specifications......................................................................................................... .....42 4.7.1 a.c. test conditions and derating curves ............................................................45 4.7.1.1 output delay or hold vs. load capacitance..........................................46 4.7.1.2 t lx vs. ad bus load capacitance.........................................................47 4.7.1.3 icc active vs. frequency ......................................................................49 4.7.2 a.c. timing waveforms .........................................................................................53 5.0 device identification ....................................................................................................................59 5.1 80960js/jc/jt device identification register....................................................................60 5.2 80960jd device identification register ..............................................................................61 5.3 80960ja/jf device identification register .........................................................................62 6.0 thermal specifications ...............................................................................................................63 6.1 thermal management accessories ....................................................................................68 6.1.1 heatsinks ...............................................................................................................68 7.0 bus functional waveforms ........................................................................................................69 7.1 basic bus states............................................................................................................ .....79 7.2 boundary-scan register.....................................................................................................8 0
contents 4 datasheet figures 1 80960jx microprocessor package options .................................................................................. 7 2 80960jx block diagram......................................................................................................... ..... 10 3 132-lead pin grid array top view-pins facing down............................................................... 23 4 132-lead pin grid array bottom view-pins facing up .............................................................. 24 5 132-lead pqfp - top view ...................................................................................................... .27 6 196-ball mini plastic ball grid array top view-balls facing down ............................................ 30 7 196-ball mini plastic ball grid array bottom view-balls facing up ........................................... 31 8 vcc5 current-limiting resistor ................................................................................................ .36 9 vccpll lowpass filter ......................................................................................................... .... 37 10 a.c. test load............................................................................................................... ............. 45 11 output delay or hold vs. load capacitance ? 80960js/jc/jt (3.3 v signals) .......................... 46 12 output delay or hold vs. load capacitance ? 80960js/jc/jt (5 v signals) ............................. 46 13 output delay or hold vs. load capacitance ? 80960ja/jf/jd .................................................... 47 14 t lx vs. ad bus load capacitance ? 80960js/jc/jt (3.3 v signals) ......................................... 47 15 t lx vs. ad bus load capacitance ? 80960js/jc/jt (5 v signals) ............................................ 48 16 t lx vs. ad bus load capacitance ? 80960ja/jf/jd................................................................... 48 17 i cc active (power supply) vs. frequency ? 80960ja/jf ............................................................. 49 18 80960ja/jf i cc active (thermal) vs. frequency ....................................................................... 49 19 80960jd i cc active (power supply) vs. frequency ................................................................... 50 20 80960jd i cc active (thermal) vs. frequency ............................................................................ 50 21 80960JC i cc active (power supply) vs. frequency ................................................................... 51 22 80960JC i cc active (thermal) vs. frequency ............................................................................ 51 23 80960js i cc active (power supply) vs. frequency ................................................................... 52 24 80960js i cc active (thermal) vs. frequency ............................................................................ 52 25 clkin waveform............................................................................................................... ......... 53 26 t ov1 output delay waveform .................................................................................................... 53 27 t of output float waveform ....................................................................................................... 54 28 t is1 and t ih1 input setup and hold waveform .......................................................................... 54 29 t is2 and t ih2 input setup and hold waveform .......................................................................... 54 30 t is3 and t ih3 input setup and hold waveform .......................................................................... 55 31 t is4 and t ih4 input setup and hold waveform .......................................................................... 55 32 t lx , t lxl and t lxa relative timings waveform ........................................................................ 56 33 dt/r# and den# timings waveform......................................................................................... 56 34 tck waveform ................................................................................................................. .......... 57 35 t bsis1 and t bsih1 input setup and hold waveforms................................................................. 57 36 t bsov1 and t bsof1 output delay and output float waveform ................................................. 57 37 t bsov2 and t bsof2 output delay and output float waveform ................................................. 58 38 t bsis2 and t bsih2 input setup and hold waveform................................................................... 58 39 80960js/jc/jt device identification register fields ................................................................. 60 40 80960jd device identification register fields ........................................................................... 61 41 80960ja/jf device identification register fields ...................................................................... 62 42 non-burst read and write transactions without wait states, 32-bit bus................................. 69 43 burst read and write transactions without wait states, 32-bit bus ........................................ 70 44 burst write transactions with 2,1,1,1 wait states, 32-bit bus .................................................. 71 45 burst read and write transactions without wait states, 8-bit bus .......................................... 72 46 burst read and write transactions with 1, 0 wait states and extra tr state on read, 16-bit bus ..................................................................................... 73 47 double word read bus request, misaligned one byte from quad word boundary, 32-bit bus, little endian ........................................................................ 74
datasheet 5 contents 48 hold/holda waveform for bus arbitration ............................................................................75 49 cold reset waveform.......................................................................................................... .......76 50 warm reset waveform .......................................................................................................... ....77 51 entering the once state...................................................................................................... ......78 52 bus states with arbitration.................................................................................................. ........80 53 summary of aligned and unaligned accesses (32-bit bus).......................................................84 54 summary of aligned and unaligned accesses (32-bit bus) (continued) ...................................85 tables 1 80960jx 3.3-v microprocessor family ......................................................................................... 7 2 80960jx instruction set ....................................................................................................... .......14 3 80960jx processors available in 132-pin pga package...........................................................15 4 80960jx processors available in 132-pin pqfp package.........................................................15 5 80960jx processors available in extended temperature .........................................................16 6 80960jx processors available in 196-ball mpbga package.....................................................16 7 pin description nomenclature .................................................................................................. ..17 8 pin description ? external bus signals.......................................................................................18 9 pin description ? processor control signals, test signals, and power .....................................21 10 pin description ? interrupt unit signals ......................................................................................22 11 132-lead pga pinout ? in signal order .....................................................................................25 12 132-lead pga pinout ? in pin order..........................................................................................26 13 132-lead pqfp pinout ? in signal order...................................................................................28 14 132-lead pqfp pinout ? in pin order........................................................................................29 15 196-ball mpbga pinout ? in signal order..................................................................................32 16 196-ball mpbga pinout ? in pin order ......................................................................................33 17 absolute maximum ratings ..................................................................................................... ...35 18 80960jx operating conditions ................................................................................................. ..35 19 vdiff parameters............................................................................................................. .........37 20 80960jx d.c. characteristics ................................................................................................. ....38 21 80960jx i cc characteristics .......................................................................................................39 22 80960jx a.c. characteristics ................................................................................................. ....42 23 note definitions for table 22, 80960jx ac characteristics........................................................45 24 80960jx device type and stepping reference .........................................................................59 25 80960js/jc/jt device id register field definitions..................................................................60 26 80960js/jc/jt device id model types .....................................................................................60 27 80960jd device id field definitions .......................................................................................... 61 28 80960jd device id model types ...............................................................................................6 1 29 80960ja/jf device id field definitions .....................................................................................62 30 80960ja/jf device id model types ..........................................................................................62 31 thermal resistance for q ca and q jc reference table ..............................................................63 32 maximum ambient temperature reference table.....................................................................63 33 132-lead pga package thermal characteristics ......................................................................64 34 80960ja/jf/jd 196-ball mpbga package thermal characteristics .........................................64 35 80960js/jc/jt 196-ball mpbga package thermal characteristics .........................................65 36 132-lead pqfp package thermal characteristics....................................................................65 37 maximum t a at various airflows in c (80960jt) ......................................................................66 38 maximum t a at various airflows in c (80960JC)......................................................................66 39 maximum t a at various airflows in c (80960jd)......................................................................67 40 maximum t a at various airflows in c (80960js) ......................................................................67 41 maximum t a at various airflows in c (80960ja/jf) .................................................................68
con t e n t s 6 d a t a s h e e t 4 2 b o un d a r y - s c a n re g i s t e r b i t o r d e r .... . ...... . ..... . ...... . ..... . ..... . ...... . ..... . ...... . ..... . ...... . ..... . ...... . ..... . . 8 1 4 3 nat u r a l b o u nda r i e s fo r l o ad an d st o r e acc e s s e s .... . ..... . ..... . ...... . ..... . ...... . ..... . ...... . ..... . ...... . ..... . . 8 1 4 4 s u mm a r y o f b y t e lo a d a n d s to r e a c c e s s e s ..... . ...... . ..... . ..... . ...... . ..... . ...... . ..... . ...... . ..... . ...... . ..... . . 8 2 4 5 s u mm a r y o f s h o r t w o r d l oad an d st o r e acc e s s e s . . ..... . ..... . ...... . ..... . ...... . ..... . ...... . ..... . ...... . ..... . . 8 2 4 6 s u mm a r y o f n - w o r d l o ad a nd st o r e acc e s s e s ( n = 1 , 2 , 3 , 4 ) ... . ..... . ...... . ..... . ...... . ..... . ...... . ..... . . 8 3 revisi o n h i story da t e rev i s i o n descr i p t io n s ep t e m ber 200 2 00 5 r emo v ed re f eren c e t o a 80960j f -16 f r o m t able 3 on pag e 1 5 . r emo v ed re f eren c e t o n g 80960 j c-40 , n g 80960 j c-33 , n g 80960 j s-16 , a nd n g 80960 j f - 16 f rom t able 4 on p ag e 1 5 . r emo v ed re f eren c e t o g d 80960 j c-40 , g d 80960 j c-33 , and 80960j s -16 i n t able 6 on p ag e 1 6 . r emo v ed re f eren c e t o 80960 j c-40 , 80960 j c-33 , 80960 j s-16 , and 8 0960j f -16 i n t able 18 on p ag e 3 5 . r emo v ed re f eren c e t o 80960 j c-40 , 80960 j c-33 , 80960 j s-16 , and 8 0960j f -16 f r o m t able 21 on p a g e 3 9 . r emo v ed re f eren c e t o 80960 j c-40 , 80960 j c-33 , 80960 j s-16 and 8 0960j f -16 f r o m t able 22 on p a g e 4 2 . s ep t e m ber 199 9 00 4 a dded new e x t ende d t emp device o f f erings . s ee t ab l e 5 on p ag e 1 6 . r e mo v ed p g a pac k age a v ailabil i t y f r o m j s / j c / j t pr o ces s o rs . c hanged a c t i m i ng p a ra m e t e r t o v 1 ( min) f o r ex t en d ed t e m p d e vices onl y . s ee t able 22 on p ag e 4 2 . june 199 9 00 3 m erged t h e 80960 j s / jc da t a s hee t in f or m a t ion in t o t his da t ashee t ( p reviousl y na m ed 809 6 0ja / j f / j d / j t 3 . 3 v e m bedded 32- b i t m i crop r oces s o r da t ash e e t ) . u pda t ed i c c values f o r t he 80 9 60js / jc / j t p r oces s o rs . i n c r eased t i h1 speci f i c a t ion f o r t h e 80960 j s / jc / j t pro c esso r s. u pda t ed m p b g a t hermal s pe c i f i c a t ion s . d e cembe r 199 8 00 2 c o rrec t ed orien t a t ion o f m p b g a p a ckage diagra m s ( f i gur e 6 on p ag e 3 0 a nd f i gure 7 on p ag e 3 1 ). a dded f i gure 1 1 on p ag e 4 6 , f i gure 1 2 on p ag e 4 6 , f i gure 14 on p ag e 4 7 , a nd f i gure 15 on p ag e 4 8 t o dis t inguish 80960 j t 3 . 3- v and 5- v s ignal d e ra t i ng cur v es f r o m t he 8 0 960ja / j f/ j d d e ra t i ng cur v es . m ar c h 199 8 00 1 t h i s da t a s hee t s u p ers ede s r e v i s i on s t o t he f o llowing 8 0 960 jx da t a s hee t s : # 273109 ( j t ) , #272971 - 002 (j d ) , and #276146 - 001 ( j a / j f ) . i n addi t i on t o c ombining t he docu m en t s in t o one , t he f ollowing c on t en t w a s c hanged : f i gure 1 o n p ag e 7 : add e d m pb g a p a c kage t o diagra m . s ec t ion 3 . 2 . 4 , 80960j x 196- b a l l m p b g a p i n o u t on pag e 3 0 : a dded new f i gure s 6 and 7 , t ables 10 , 1 1 a n d 13 . f i gure 16 o n p ag e 4 8 : a d ded wi t h t he no t e t ha t f ol l ow s t he f i gure . august 200 4 00 6 to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
8 0 960 j a / j f / j d / j s /jc / j t 3 . 3 v e m b e dd e d 32 - b i t m i cr op r o c es s o r da t as h e e t 7 1 . 0 i n t r o d u c t i o n th i s d o cume n t con t a i n s i n f o rm a t i o n f o r t h e 80 9 60 j x m i c rop r oce s s o r s , i n c l u d ing e lec t r ica l cha r ac t e r i s ti c s and packa g e p i n o u t i n f o rma ti o n . d e t a il e d f u nc ti o n a l de s c r i p tion s , o ther t h an pa r a me t r i c pe r for m a nce, a r e p u b li s h e d i n t h e i96 0 ? jx m i c r o p r o ce s s o r develop e r s m a nu a l (2 7 2 4 83) a nd ma y b e v i e w e d on li n e a t h tt p :/ / d e v e l o p e r . i n tel.c o m / d e s i g n /i96 0 / t ec h i n f o / 8 09 6 0 j x/ . t h r ou g ho u t t h i s d a ta s h eet, r e f e r e n ce s t o 80 9 60 j x indicate f ea t u r e s that ap p ly to t h e 3 . 3-v j x pr o ce s s o r s o n ly : f igu r e 1 . 8 0 96 0 jx m i c r o p r o ce s s o r p a c ka g e o pt ion s i 9 6 0 ? i m i ? 1 9 x x m ? 19x x x 8 09 6 0j x x 809 6 0j x x xxx x xxx s s xxx x xxxx ss i m ? 1 9x x x 809 6 0j x xx x xx x x s s 132 - p i n p g a 132 - p i n p qf p 196- b a l l m p b g a t a b l e 1 . 8 0 96 0 jx 3 . 3 - v mi c r op r o c e ss o r f am ily pr o cess o r v o l t a g e in str u c t i on c ac h e da t a cac h e core cloc k 80960 j a 3 . 3 v ( 5 v t o ler a n t ) 2 k b y t e 1 kb y t e 1 x 80960j f 3 . 3 v ( 5 v t o ler a n t ) 4 k b y t e 2 kb y t e 1 x 80960 j d 3 . 3 v ( 5 v t o ler a n t ) 4 k b y t e 2 kb y t e 2 x 80960 j s 3 . 3 v ( 5 v t o ler a n t ) 16 kby t e 4 kb y t e 1 x 80960 j c 3 . 3 v ( 5 v t o ler a n t ) 16 kby t e 4 kb y t e 2 x 80960j t 3 . 3 v ( 5 v t o ler a n t ) 16 kby t e 4 kb y t e 3 x note: to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
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80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 9 2.0 80960jx overview the 80960jx processor offers high performance to cost-sensitive 32-bit embedded applications. the 80960jx is object code compatible with the 80960 core architecture and is capable of sustained execution at the rate of one instruction per clock. this processor ? s features include generous instruction cache, data cache, and data ram. it also boasts a fast interrupt mechanism and dual-programmable timer units. the 80960jx processor ? s clock multiplication operates the processor core at two or three times the bus clock rate to improve execution performance without increasing the complexity of board designs. memory subsystems for cost-sensitive embedded applications often impose substantial wait state penalties. the 80960jx integrates considerable storage resources on-chip to decouple cpu execution from the external bus. the 80960jx rapidly allocates and de-allocates local register sets during context switches. the processor must flush a register set to the stack only when it saves more than seven sets to its local register cache. a 32-bit multiplexed burst bus provides a high-speed interface to system memory and i/o. a full complement of control signals simplifies the connection of the 80960jx to external components. the user programs physical and logical memory attributes through memory-mapped control registers (mmrs), an extension not found on the i960 ? kx, sx or cx processors. physical and logical configuration registers enable the processor to operate with all combinations of bus width and data object alignment. the processor supports a homogeneous byte ordering model. this processor integrates two important peripherals: a timer unit and an interrupt controller. these and other hardware resources are programmed through memory-mapped control registers, an extension to the familiar i960 processor architecture. the timer unit (tu) offers two independent 32-bit timers for use as real-time system clocks and general-purpose system timing. these operate in either single-shot or auto-reload mode and may generate interrupts. the interrupt controller unit (icu) provides a flexible, low-latency means for requesting interrupts. the icu provides full programmability of up to 240 interrupt sources into 31 priority levels. the icu takes advantage of a cached priority table and optional routine caching to minimize interrupt latency. clock doubling on the 80960jd/jc processors reduces interrupt latency by 40% compared to the 80960ja/jf, and clock tripling on the 80960jt reduces interrupt latency by 20% compared to the 80960jd/jc. local registers may be dedicated to high-priority interrupts to further reduce latency. acting independently from the core, the icu compares the priorities of posted interrupts with the current process priority, off-loading this task from the core. the icu also supports the integrated timer interrupts. the 80960jx features a halt mode designed to support applications where low power consumption is critical. the halt instruction shuts down instruction execution, resulting in a power savings of up to 90 percent. the 80960jx ? s testability features, including once (on-circuit emulation) mode and boundary scan (jtag), provide a powerful environment for design debug and fault diagnosis.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 10 datasheet the solutions960 ? program features a wide variety of development tools which support the i960 processor family. many of these tools are developed by partner companies; some are developed by intel, such as profile-driven optimizing compilers. for more information on these products, contact your local intel representative. 2.1 80960 processor core the 80960jx family is a scalar implementation of the 80960 core architecture. intel designed this processor core as a very high performance device that is also cost-effective. factors that contribute to the core ? s performance include: core operates at the bus speed with the 80960ja/jf/js core operates at two or three times the bus speed with the 80960jd/jc and 80960jt, respectively single-clock execution of most instructions independent multiply/divide unit efficient instruction pipeline minimizes pipeline break latency register and resource scoreboarding allow overlapped instruction execution 128-bit register bus speeds local register caching two-way set associative, integrated instruction cache direct-mapped, integrated data cache 1-kbyte integrated data ram delivers zero wait state program data figure 2. 80960jx block diagram programmable interrupt controller control address/ instruction sequencer physical region configuration interrupt port 1k data ram memory interface execution multiply unit divide unit memory-mapped register interface data bus global / local register file src2 dest src1 address control effective constants generation unit address 32-bit address 32-bit data bus request queues and two 32-bit timers 8-set local register cache src1 src2 dest pll, clocks, power mgmt boundary scan controller tap 5 clkin src1 src2 dest src1 dest 9 32 32-bit buses address / data 21 instruction cache 80960ja - 2k 80960jf/jd - 4k 80960js/jc/jt - 16k direct mapped data cache 80960ja - 1k 80960jf/jd - 2k 80960js/jc/jt - 128 3 independent 32-bit src1, src2, and dest buses bus control unit
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 11 2.2 burst bus a 32-bit high-performance bus controller unit (bcu) interfaces the 80960jx to external memory and peripherals. the bcu fetches instructions and transfers data at the rate of up to four 32-bit words per six clock cycles. the external address/data bus is multiplexed. users may configure the 80960jx ? s bus controller to match an application ? s fundamental memory organization. physical bus width is register-programmed for up to eight regions. byte ordering and data caching are programmed through a group of logical memory templates and a defaults register. the bcu ? s features include: multiplexed external bus to minimize pin count 32-, 16-, and 8-bit bus widths to simplify i/o interfaces external ready control for address-to-data, data-to-data and data-to-next-address wait state types support for big or little endian byte ordering to facilitate the porting of existing program code unaligned bus accesses performed transparently three-deep load/store queue to decouple the bus from the core upon reset, the 80960jx conducts an internal self-test. then, before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the initialization boot record (ibr). 2.3 timer unit the timer unit (tu) contains two independent 32-bit timers that are capable of counting at several clock rates and generating interrupts. each is programmed by use of the tu registers. these memory-mapped registers are addressable on 32-bit boundaries. the timers have a single-shot mode and auto-reload capabilities for continuous operation. each timer has an independent interrupt request to the 80960jx ? s interrupt controller. the tu may generate a fault when unauthorized writes from user mode are detected. clock prescaling is supported. 2.4 priority interrupt controller a programmable interrupt controller manages up to 240 external sources through an 8-bit external interrupt port. alternatively, the interrupt inputs may be configured for individual edge- or level- triggered inputs. the interrupt unit (iu) also accepts interrupts from the two on-chip timer channels and a single non-maskable interrupt (nmi#) pin. interrupts are serviced according to their priority levels relative to the current process priority. low interrupt latency is critical to many embedded applications. as part of its highly flexible interrupt mechanism, the 80960jx exploits several techniques to minimize latency: interrupt vectors and interrupt handler routines may be reserved on-chip. register frames for high-priority interrupt handlers may be cached on-chip. the interrupt stack may be placed in cacheable memory space. interrupt microcode executes at two or three times the bus frequency for the 80960jd/jc and 80960jt, respectively.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 12 datasheet 2.5 instruction set summary the 80960jx adds several new instructions to the i960 processor core architecture. the new instructions are: conditional move conditional add conditional subtract byte swap halt cache control interrupt control table 2 identifies the instructions that the 80960jx supports. refer to the i960 ? jx microprocessor developer ? s manual (272483) for a detailed description of each instruction. 2.6 faults and debugging the 80960jx employs a comprehensive fault model. the processor responds to faults by making implicit calls to a fault handling routine. specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately. the processor also has built-in debug capabilities. in software, the 80960jx may be configured to detect as many as seven different trace event types. alternatively, mark and fmark instructions may generate trace events explicitly in the instruction stream. hardware breakpoint registers are also available to trap on execution and data addresses. 2.7 low power operation intel fabricates the 80960jx using an advanced sub-micron manufacturing process. the processor ? s sub-micron topology provides the circuit density for optimal cache size and high operating speeds while dissipating modest power. the processor also uses dynamic power management to turn off clocks to unused circuits. users may program the 80960jx to enter halt mode for maximum power savings. in halt mode, the processor core stops completely while the integrated peripherals continue to function, reducing overall power requirements up to 90 percent. processor execution resumes from internally or externally generated interrupts. 2.8 test features the 80960jx incorporates numerous features that enhance the user ? s ability to test both the processor and the system to which it is attached. these features include once (on-circuit emulation) mode and boundary scan (jtag).
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 13 the 80960jx provides testability features compatible with ieee standard test access port and boundary scan architecture (ieee std. 1149.1). one of the boundary scan instructions, highz, forces the processor to float all its output pins (once mode). once mode may also be initiated at reset without using the boundary scan mechanism. once mode is useful for board-level testing. this feature allows a mounted 80960jx to electrically ? remove ? itself from a circuit board. this allows for system-level testing in which a remote tester, such as an in-circuit emulator, may exercise the processor system. the provided test logic does not interfere with component or circuit board behavior and ensures that components function correctly, connections between various components are correct, and various components interact correctly on the printed circuit board. the jtag boundary scan feature is an attractive alternative to conventional ? bed-of-nails ? testing. it may examine connections that might otherwise be inaccessible to a test system. 2.9 memory-mapped control registers the 80960jx, although compliant with the i960 processor core, has the added advantage of memory-mapped, internal control registers not found on the i960 kx, sx or cx processors. these registers give software the interface to easily read and modify internal control registers. each of these registers is accessed as a memory-mapped, 32-bit register. access is accomplished through regular memory-format instructions. the processor ensures that these accesses do not generate external bus cycles. 2.10 data types and memory addressing modes as with all i960 processors, the 80960jx instruction set supports several data types and formats: bit bit fields integer (8-, 16-, 32-, 64-bit) ordinal (8-, 16-, 32-, 64-bit unsigned integers) triple word (96 bits) quad word (128 bits) the 80960jx provides a full set of addressing modes for c and assembly programming: two absolute modes five register indirect modes index with displacement ip with displacement
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 14 datasheet table 2. 80960jx instruction set data movement arithmetic logical bit, bit field and byte load store move conditional select ? load address add subtract multiply divide remainder modulo shift extended shift extended multiply extended divide add with carry subtract with carry conditional add ? conditional subtract ? rotate and not and and not or exclusive or not or or not nor exclusive nor not nand set bit clear bit not bit alter bit scan for bit span over bit extract modify scan byte for equal byte swap ? comparison branch call/return fault compare conditional compare compare and increment compare and decrement test condition code check bit unconditional branch conditional branch compare and branch call call extended call system return branch and link conditional fault synchronize faults debug processor management atomic modify trace controls mark force mark flush local registers modify arithmetic controls modify process controls halt ? system control cache control ? interrupt control ? atomic add atomic modify ? denotes new 80960 instructions unavailable on 80960ca/cf, 80960ka/kb and 80960sa/sb processors.
8 0 960 j a / j f / j d / j s /jc / j t 3 . 3 v e m b e dd e d 32 - b i t m i cr op r o c es s o r da t as h e e t 1 5 3 . 0 p acka g in g information 3 . 1 a va i l a b l e p r o c ess o r s a nd p acka g e s t h e 80 9 60 j x i s o f f e r e d i n v a r i o u s s p ee d g r a d e s a n d t h r ee p ac k a g e typ e s . the 13 2 -pin p i n grid ar r a y (pga) d e vice i s s p ec i f ied f o r o p eratio n at v c c = 3 . 3 v 0 . 1 5 v o v e r a ca s e tempe r a t u r e r a nge o f 0 c t o 1 0 0 c . t h e foll o w i n g p r oce s s o r ve r s i o n s are a v a i la b l e in the p g a p ac k a g e : for p ino u t diagr a m s f o r t h e pg a packa g e, s ee s ec t i o n 3 . 2. 2 , 8 0 96 0 j x 1 3 2-lea d p g a p i n o u t o n pa g e 2 3 . t h e 13 2 -p i n p l a s t i c q u a d f lat p ac k (pq f p) d ev ice s a r e s p eci f ie d fo r op e r at i o n at v c c = 3 . 3 v 0. 1 5 v o v e r a ca s e t e m p e r at u r e r a n g e o f 0 c t o 1 0 0 c . t a b l e 4 pre s en t s 8 0 96 0 j x pr o ce s s o r v e r s i o n s t h at a r e a v a i la b l e i n t h e 1 32 - p i n pqf p p ac k a g e : for pin o ut diagra m s o f the pq f p packa g e, s ee s ec t i o n 3. 2 . 3, 8 0 96 0 j x 1 3 2 - lead p q f p p i n o u t on pa g e 2 7 . exte n d ed te m p e r atu r e de v i ce s a r e s p eci f ied f o r o p e r atio n at v c c = 3 .3 v 0. 1 5 v o v e r a ca s e tempe r a t u r e r a nge o f - 4 0 c t o 1 0 0 c . t a b l e 5 pre s ent s 8 0 96 0 j x pr o ce s s o r ver s io n s t h a t are available i n the e x t e n d ed t e m p e r at u r e 1 3 2 - p in pq f p p ackage an d mp b ga p ac k a g e : t a b l e 3 . 8 0 96 0 jx p r o c es s o r s a v a il a b l e i n 1 32 - p i n p g a p a c ka g e p r o ces s o r c o re s p ee d b u s s p ee d x 80960j d - 6 6 66 m h z 33 mh z x 80960j d - 3 3 33 m h z 16 mh z x 80960j a / j f - 3 3 33 m h z 33 mh z x80960jf-25 25 mhz 25 mhz t a b l e 4. 8 0 96 0 jx p r o c es s o r s a v ail a b l e i n 1 32 - p i n p q f p p a cka g e p r o ces s o r c o re s p ee d b u s s p ee d x 8 0 960j t -10 0 100 m h z 33 mh z x 8 0 960jc-6 6 66 m h z 33 mh z x 8 0 960jc-5 0 50 m h z 25 mh z x 8 0 960 js - 3 3 33 m h z 33 m h z x 8 0 960 js - 2 5 25 m h z 25 m h z x 8 0 960jd-6 6 66 m h z 33 mh z x 8 0 960jd-4 0 40 m h z 20 mh z x 8 0 960ja / j f -3 3 33 m h z 33 mh z x 8 0 960ja / j f -2 5 25 m h z 25 mh z x 8 0 960 ja - 1 6 16 m h z 16 m h z note: to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
80 9 60 j a / j f / j d / j s /jc / j t 3 . 3 v e m b e dd e d 3 2 - b i t m i cr op r o c es s o r 1 6 d a t a s h e e t the 1 96 - ball mini p l a s tic b all gri d arra y (mp b ga) d evice i s s p ecified f o r o p eratio n a t v cc = 3 . 3 v 0.1 5 v o v er a ca s e tem p erature ran g e of 0 c t o 1 0 0 c. t a b l e 6 p r e s ent s the 80 9 60 j x p r oce ss o r v e r s ion s that a r e available in t h e 1 9 6- b a l l m p b g a packa g e : f o r p i n out diag r a m s of the pqf p packa g e, s ee s ec tion 3. 2 . 4, 80 9 6 0 jx 1 9 6- b a l l mp b ga p i n o u t on p a g e 3 0 . f o r ad d i t i o n al pac k age s p eci f icati o n s an d i n fo r m at i o n , r ef e r t o t h e i n t e l pack a g i n g d a tab o o k , available in i n divid u al cha p t e r s , a t h tt p :// w w w .i n tel.c o m . 3 . 2 p in d e sc ript i o n s th i s sec ti o n de s c r ibe s t h e p i n s fo r t h e 8 09 6 0 j x p roce s s o r s . f o r a de s c r i p tion of p i n f u nc ti o n , s ee s ec ti o n 3 . 2 . 1 , f u nc tiona l p i n d e f i n it i o n s o n pa g e 1 6 . r e f e r t o t h e fo ll o w i n g s ec t i o n s fo r p i n o u t i n fo r m ation f o r t h e three packa g e type s : ? s ec ti o n 3 . 2 . 2 , 80 9 60 j x 13 2 -lead p ga p ino u t on pag e 2 3 . ? s ec ti o n 3 . 2 . 3 , 80 9 60 j x 13 2 -lead p q f p p i n ou t o n p a g e 2 7 . ? s ec ti o n 3 . 2 . 4 , 8 0 9 60 j x 1 9 6 - ba ll m p b ga p i n o u t o n pag e 3 0 . 3.2 . 1 f unc t i onal p i n definitions t a b l e 7 p r e s e n t s t h e le g e n d f o r i n te r p r e ti ng t h e t h r ee p i n d e s c r i p t i o n ta b l e s t h at f o l l o w . t h e s e ta b l e s define t h e pi n s a ss o ciated w ith the bu s inter f ace, ba s ic c o ntrol a n d te s t fu n c t i o n s , an d the i n terr u pt u n i t . t a b l e 5 . 8 09 6 0j x p r o ce s s o rs a vai l a b l e i n ex t e n d e d t e m p er a t u r e pr o cess o r c o r e s p ee d b u s s p ee d packa g e t y p e x 809 6 0ja - 2 5 25 mh z 25 m h z pqf p x 809 6 0js - 2 5 25 mh z 25 m h z pqf p x 809 6 0js - 3 3 33 mh z 33 m h z pqf p x 809 6 0 j c-6 6 66 mh z 33 m h z pqf p x 809 6 0j t -10 0 100 mh z 33 m h z pqf p x 80960 j c - 66 e t 66 m h z 33 m h z m p b g a t a b l e 6 . 8 09 6 0j x p r o ce s s o rs a va i l a b l e i n 19 6 - b a ll m p b g a p a c ka g e pr o cess o r c o r e s p ee d b u s s p ee d x 80960j t - 10 0 100 mh z 33 m h z x 80960JC - 6 6 66 mh z 33 m h z x 80960j s - 3 3 33 mh z 33 m h z x 80960j s - 2 5 25 mh z 25 m h z x 80960jd - 5 0 50 mh z 25 m h z x80960ja/jf-33 33 mhz 33 mhz note: to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 17 table 7. pin description nomenclature symbol description i input pin only. o output pin only. i/o pin may be either an input or output. ? pin must be connected as described. s synchronous. inputs must meet setup and hold times relative to clkin for proper operation. s(e) edge sensitive input s(l) level sensitive input a (...) asynchronous. inputs may be asynchronous relative to clkin. a(e) edge sensitive input a(l) level sensitive input r (...) while the processor ? s reset# pin is asserted, the pin: r(1) is driven to v cc r(0) is driven to v ss r(q) is a valid output r(x) is driven to unknown state r(h) is pulled up to v cc h (...) while the processor is in the hold state, the pin: h(1) is driven to v cc h(0) is driven to v ss h(q) maintains previous state or continues to be a valid output h(z) floats p (...) while the processor is halted, the pin: p(1) is driven to v cc p(0) is driven to v ss p(q) maintains previous state or continues to be a valid output
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 18 datasheet table 8. pin description ? external bus signals (sheet 1 of 4) name type description ad[31:0] i/o s(l) r(x) h(z) p(q) address / data bus carries 32-bit physical addresses and 8-, 16- or 32-bit data to and from memory. during an address ( t a ) cycle, bits 31:2 contain a physical word address (bits 0-1 indicate size; see below). during a data (t d ) cycle, read or write data is present on one or more contiguous bytes, comprising ad[31:24], ad[23:16], ad[15:8] and ad[7:0]. during write operations, unused pins are driven to determinate values. size, which comprises bits 0-1 of the ad lines during a t a cycle, specifies the number of data transfers during the bus transaction. ad1 ad0 bus transfers 0 0 1 transfer 0 1 2 transfers 1 0 3 transfers 1 1 4 transfers when the processor enters halt mode, if the previous bus operation was a: write ? ad[31:2] are driven with the last data value on the ad bus. read ? ad[31:4] are driven with the last address value on the ad bus; ad[3:2] are driven with the value of a[3:2] from the last data cycle. typically, ad[1:0] reflect the size information of the last bus transaction (either instruction fetch or load/store) that was executed before entering halt mode. ale o r(0) h(z) p(0) address latch enable indicates the transfer of a physical address. ale is asserted during a t a cycle and deasserted before the beginning of the t d state. it is active high and floats to a high impedance state during a hold cycle (t h ). ale# o r(1) h(z) p(1) address latch enable indicates the transfer of a physical address. ale# is the inverted version of ale. this signal gives the 80960jx a high degree of compatibility with existing 80960kx systems. ads# o r(1) h(z) p(1) address strobe indicates a valid address and the start of a new bus access. the processor asserts ads# for the entire t a cycle. external bus control logic typically samples ads# at the end of the cycle. a[3:2] o r(x) h(z) p(q) address[3:2] comprise a partial demultiplexed address bus. 32-bit memory accesses: the processor asserts address bits a[3:2] during t a . the partial word address increments with each assertion of rdyrcv# during a burst. 16-bit memory accesses: the processor asserts address bits a[3:1] during t a with a1 driven on the be1# pin. the partial short word address increments with each assertion of rdyrcv# during a burst. 8-bit memory accesses: the processor asserts address bits a[3:0] during t a , with a[1:0] driven on be[1:0]#. the partial byte address increments with each assertion of rdyrcv# during a burst.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 19 be[3:0]# o r(1) h(z) p(1) byte enables select which of up to four data bytes on the bus participate in the current bus access. byte enable encoding is dependent on the bus width of the memory region accessed: 32-bit bus: be3# enables data on ad[31:24] be2# enables data on ad[23:16] be1# enables data on ad[15:8] be0# enables data on ad[7:0] 16-bit bus: be3# becomes byte high enable (enables data on ad[15:8]) be2# is not used (state is high) be1# becomes address bit 1 (a1) be0# becomes byte low enable (enables data on ad[7:0]) 8-bit bus: be3# is not used (state is high) be2# is not used (state is high) be1# becomes address bit 1 (a1) be0# becomes address bit 0 (a0) the processor asserts byte enables, byte high enable and byte low enable during t a . since unaligned bus requests are split into separate bus transactions, these signals do not toggle during a burst. they remain active through the last t d cycle. for accesses to 8- and 16-bit memory, the processor asserts the address bits in conjunction with a[3:2] described above. width/ hltd[1:0] o r(0) h(z) p(1) width/halted signals denote the physical memory attributes for a bus transaction: width/ hltd1 width/ hltd0 0 0 8 bits wide 0 1 16 bits wide 1 0 32 bits wide 1 1 processor halted the processor floats the width/hltd pins whenever it relinquishes the bus in response to a hold request, regardless of prior operating state. d/c# o r(x) h(z) p(q) data/code indicates that a bus access is a data access (1) or an instruction access (0). d/c# has the same timing as w/r#. 0 = instruction access 1 = data access w/r# o r(0) h(z) p(q) write/read specifies, during a t a cycle, whether the operation is a write (1) or read (0). it is latched on-chip and remains valid during t d cycles. 0 = read 1 = write dt/r# o r(0) h(z) p(q) data transmit / receive indicates the direction of data transfer to and from the address/data bus. it is low during t a and t w /t d cycles for a read; it is high during t a and t w /t d cycles for a write. dt/r# never changes state when den# is asserted. 0 = receive 1 = transmit table 8. pin description ? external bus signals (sheet 2 of 4) name type description
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 20 datasheet den# o r(1) h(z) p(1) data enable indicates data transfer cycles during a bus access. den# is asserted at the start of the first data cycle in a bus access and deasserted at the end of the last data cycle. den# is used with dt/r# to provide control for data transceivers connected to the data bus. 0 = data cycle 1 = not data cycle blast# o r(1) h(z) p(1) burst last indicates the last transfer in a bus access. blast# is asserted in the last data transfer of burst and non-burst accesses. blast# remains active as long as wait states are inserted through the rdyrcv# pin. blast# becomes inactive after the final data transfer in a bus cycle. 0 = last data transfer 1 = not last data transfer rdyrcv# i s(l) ready/recover indicates that data on ad lines may be sampled or removed. when rdyrcv# is not asserted during a t d cycle, the t d cycle is extended to the next cycle by inserting a wait state (t w ). 0 = sample data 1 = don ? t sample data the rdyrcv# pin has another function during the recovery (t r ) state. the processor continues to insert additional recovery states until it samples the pin high. this function gives slow external devices more time to float their buffers before the processor begins to drive address again. 0 = insert wait states 1 = recovery complete lock#/ once# i/o s(l) r(h) h(z) p(1) bus lock indicates that an atomic read-modify-write operation is in progress. the lock# output is asserted in the first clock of an atomic operation and deasserted in the last data transfer of the sequence. the processor does not grant holda while it is asserting lock#. this prevents external agents from accessing memory involved in semaphore operations. 0 = atomic read-modify-write in progress 1 = atomic read-modify-write not in progress once mode: the processor samples the once# input during reset. when it is asserted low at the end of reset, the processor enters once mode. in once mode, the processor stops all clocks and floats all output pins. the pin has a weak internal pullup which is active during reset to ensure normal operation when the pin is left unconnected. 0 = once mode enabled 1 = once mode not enabled hold i s(l) hold : a request from an external bus master to acquire the bus. when the processor receives hold and grants bus control to another master, it asserts holda, floats the address/data and control lines and enters the t h state. when hold is deasserted, the processor deasserts holda and enters either the t i or t a state, resuming control of the address/data and control lines. 0 = no hold request 1 = hold request table 8. pin description ? external bus signals (sheet 3 of 4) name type description
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 21 holda o r(q) h(1) p(q) hold acknowledge indicates to an external bus master that the processor has relinquished control of the bus. the processor may grant hold requests and enter the t h state during reset and while halted as well as during regular operation. 0 = hold not acknowledged 1 = hold acknowledged bstat o r(0) h(q) p(0) bus status indicates that the processor may soon stall unless it has sufficient access to the bus; see i960 ? jx microprocessor developer ? s manual (272483). arbitration logic may examine this signal to determine when an external bus master should acquire/relinquish the bus. 0 = no potential stall 1 = potential stall table 9. pin description ? processor control signals, test signals, and power (sheet 1 of 2) name type description clkin i clock input provides the processor ? s fundamental time base; both the processor core and the external bus run at the clkin rate. all input and output timings are specified relative to a rising clkin edge. reset# i a(l) reset initializes the processor and clears its internal logic. during reset, the processor places the address/data bus and control output pins in their idle (inactive) states. during reset, the input pins are ignored with the exception of lock#/once#, stest and hold. the reset# pin has an internal synchronizer. to ensure predictable processor initialization during power up, reset# must be asserted a minimum of 10,000 clkin cycles with v cc and clkin stable. on a warm reset, reset# should be asserted for a minimum of 15 cycles. stest i s(l) self test enables or disables the processor ? s internal self-test feature at initialization. stest is examined at the end of reset. when stest is asserted, the processor performs its internal self-test and the external bus confidence test. when stest is deasserted, the processor performs only the external bus confidence test. 0 = self test disabled 1 = self test enabled fail# o r(0) h(q) p(1) fail indicates a failure of the processor ? s built-in self-test performed during initialization. fail# is asserted immediately upon reset and toggles during self-test to indicate the status of individual tests: when self-test passes, the processor deasserts fail# and begins operation from user code. when self-test fails, the processor asserts fail# and then stops executing. 0 = self test failed 1 = self test passed tck i test clock is a cpu input which provides the clocking function for ieee 1149.1 boundary scan testing (jtag). state information and data are clocked into the processor on the rising edge; data is clocked out of the processor on the falling edge. tdi i s(l) test data input is the serial input pin for jtag. tdi is sampled on the rising edge of tck, during the shift-ir and shift-dr states of the test access port. table 8. pin description ? external bus signals (sheet 4 of 4) name type description
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 22 datasheet tdo o r(q) hq) p(q) test data output is the serial output pin for jtag. tdo is driven on the falling edge of tck during the shift-ir and shift-dr states of the test access port. at other times, tdo floats. tdo does not float during once mode. trst# i a(l) test reset asynchronously resets the test access port (tap) controller function of ieee 1149.1 boundary scan testing (jtag). when using the boundary scan feature, connect a pull-down resistor between this pin and v ss . when tap is not used, this pin must be connected to v ss ; however, no resistor is required. see section 4.3, ? connection recommendations ? on page 36 . tms i s(l) test mode select is sampled at the rising edge of tck to select the operation of the test logic for ieee 1149.1 boundary scan testing. v cc ? power pins intended for external connection to a v cc board plane. vccpll ? pll power is a separate v cc supply pin for the phase lock loop clock generator. it is intended for external connection to the v cc board plane. in noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. vcc5 ? 5 v reference voltage input is the reference voltage for the 5 v-tolerant i/o buffers. this signal should be connected to +5 v for use with inputs which exceed 3.3 v. when all inputs are from 3.3 v components, this pin should be connected to 3.3 v. v ss ? ground pins intended for external connection to a v ss board plane. nc ? no connect pins. do not make any system connections to these pins. table 10. pin description ? interrupt unit signals name type description xint[7:0]# i a(e/l) external interrupt pins are used to request interrupt service. the xint[7:0]# pins may be configured in three modes: dedicated mode : each pin is assigned a dedicated interrupt level. dedicated inputs may be programmed to be level (low) or edge (falling) sensitive. expanded mode : all eight pins act as a vectored interrupt source. the interrupt pins are level sensitive in this mode. mixed mode : the xint[7:5]# pins act as dedicated sources and the xint[4:0]# pins act as the five most significant bits of a vectored source. the least significant bits of the vectored source are set to 010 2 internally. unused external interrupt pins should be connected to v cc . nmi# i a(e) non-maskable interrupt causes a non-maskable interrupt event to occur. nmi# is the highest priority interrupt source and is falling edge-triggered. when nmi# is unused, it should be connected to v cc . table 9. pin description ? processor control signals, test signals, and power (sheet 2 of 2) name type description
8 0 960 j a / j f / j d / j s /jc / j t 3 . 3 v e m b e dd e d 32 - b i t m i cr op r o c es s o r da t as h e e t 2 3 3 . 2 . 2 8 0 9 6 0j x 132-lead p g a pinout f igu r e 3 . 1 3 2 -l ea d p i n g r i d arr a y t op v i e w - p i n s f a c i n g d o w n a d 6 a d 1 1 a d 1 3 v c c v c c v c c v c c v c c v c c v c c a d 1 8 a d 1 9 a d 2 2 ad 2 5 a d 3 a d 7 a d 1 0 v s s v s s v s s v s s v s s v s s v s s a d 2 0 a d 2 4 a d 2 6 ad 2 7 a d 0 a d 4 a d 8 ad 9 a d 1 2 ad 1 4 a d 1 5 ad 1 6 a d 1 7 ad 2 1 ad 2 3 a d 2 9 a d 3 0 n c a d 2 8 be 3 # b e 2 # a d 3 1 v s s v c c be 1 # v s s v c c be 0 # v s s v c c a l e v c c b s t a t v s s v c c v s s v c c d t / r # v s s v c c v c c a d 1 v c c v s s v c c v s s n c c l k i n v s s v ccp l l v c c v s s n c v c c rd y rcv # v c c r e se t # v c c v s s a d 5 a d 2 v s s t d i x i n t 0 # n c a 2 w i d t h / a d s # a 3 x i n t 1 # t m s x i n t 2 # n c s t e s t t rs t # ho l d n c f a i l # v c c 5 b l a s t # l o c k # / ho l d a t c k x i n t 3 # x i n t 5 # xi n t 7 # n m i # v c c v c c v c c v c c n c n c a l e # x i n t 6 # v s s v s s v s s v s s n c t d o w id t h / d /c # w /r# x i n t 4 # p n m l k j h g f e d c b a p n m l k j h g f e d c b a 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 v s s d e n # v s s h l t d 1 h l t d 0 onc e # i ? 1 9x x x80960jx xxxx x xx x ss m note: to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 24 datasheet figure 4. 132-lead pin grid array bottom view-pins facing up ad6 ad11 ad13 v cc v cc v cc v cc v cc v cc v cc ad18 ad19 ad22 ad25 ad3 ad7 ad10 v ss v ss v ss v ss v ss v ss v ss ad20 ad24 ad26 ad27 ad0 ad4 ad8 ad9 ad12 ad14 ad15 ad16 ad17 ad21 ad23 ad29 ad30 nc ad28 be3# be2# ad31 v ss v cc be1# v ss v cc be0# v ss v cc ale v cc bstat v ss v cc v ss v cc dt/r# v ss v cc v cc ad1 v cc v ss v cc v ss nc clkin v ss vccpll v cc v ss nc v cc rdyrcv# v cc reset# v cc v ss ad5 ad2 v ss tdi xint0# nc a2 width/ ads# a3 xint1# tms xint2# nc stest trst# hold nc fail# vcc5 blast# lock#/ holda tck xint3# xint5# xint7# nmi# v cc v cc v cc v cc nc nc ale# xint6# v ss v ss v ss v ss nc tdo width/ d/c# w/r# xint4# p n m l k j h g f e d c b a p n m l k j h g f e d c b a 14 13 12 11 10 9 8 7 6 5 4 3 2 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v ss den# v ss hltd1 hltd0 once#
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 25 table 11. 132-lead pga pinout ? in signal order signal pin signal pin signal pin signal pin a2 c5 ad31 k3 tdo b4 v ss b9 a3 c4 ads# a1 tms a14 v ss d2 ad0 m14 ale g3 trst# c12 v ss d13 ad1 l13 ale# a3 v cc a6 v ss e2 ad2 k12 be0# h3 v cc a7 v ss e13 ad3 n14 be1# j3 v cc a8 v ss f2 ad4 m13 be2# l1 v cc a9 v ss f13 ad5 l12 be3# l2 v cc d1 v ss g2 ad6 p14 blast# c3 v cc d14 v ss g13 ad7 n13 bstat f3 v cc e1 v ss h2 ad8 m12 clkin h14 v cc e14 v ss h13 ad9 m11 d/c# b2 v cc f1 v ss j2 ad10 n12 den# e3 v cc f14 v ss j13 ad11 p13 dt/r# d3 v cc g1 v ss k2 ad12 m10 fail# c6 v cc g14 v ss k13 ad13 p12 hold c9 v cc h1 v ss n5 ad14 m9 holda c2 v cc j1 v ss n6 ad15 m8 lock#/once# c1 v cc j14 v ss n7 ad16 m7 nc a4 v cc k1 v ss n8 ad17 m6 nc a5 v cc k14 v ss n9 ad18 p4 nc b5 v cc l14 v ss n10 ad19 p3 nc b14 v cc p5 v ss n11 ad20 n4 nc c8 v cc p6 w/r# b1 ad21 m5 nc c14 v cc p7 width/hltd0 b3 ad22 p2 nc g12 v cc p8 width/hltd1 a2 ad23 m4 nc j12 v cc p9 xint0# c11 ad24 n3 nc m3 v cc p10 xint1# c10 ad25 p1 nmi# a10 v cc p11 xint2# a13 ad26 n2 rdyrcv# f12 vccpll h12 xint3# b12 ad27 n1 reset# e12 vcc5 c7 xint4# b11 ad28 l3 stest c13 v ss b6 xint5# a12 ad29 m2 tck b13 v ss b7 xint6# b10 ad30 m1 tdi d12 v ss b8 xint7# a11 note: do not connect any external logic to pins marked nc (no connect pins).
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 26 datasheet table 12. 132-lead pga pinout ? in pin order pin signal pin signal pin signal pin signal a1 ads# c6 fail# h1 v cc m10 ad12 a2 width/hltd1 c7 vcc5 h2 v ss m11 ad9 a3 ale# c8 nc h3 be0# m12 ad8 a4 nc c9 hold h12 vccpll m13 ad4 a5 nc c10 xint1# h13 v ss m14 ad0 a6 v cc c11 xint0# h14 clkin n1 ad27 a7 v cc c12 trst# j1 v cc n2 ad26 a8 v cc c13 stest j2 v ss n3 ad24 a9 v cc c14 nc j3 be1# n4 ad20 a10 nmi# d1 v cc j12 nc n5 v ss a11 xint7# d2 v ss j13 v ss n6 v ss a12 xint5# d3 dt/r# j14 v cc n7 v ss a13 xint2# d12 tdi k1 v cc n8 v ss a14 tms d13 v ss k2 v ss n9 v ss b1 w/r# d14 v cc k3 ad31 n10 v ss b2 d/c# e1 v cc k12 ad2 n11 v ss b3 width/hltd0 e2 v ss k13 v ss n12 ad10 b4 tdo e3 den# k14 v cc n13 ad7 b5 nc e12 reset# l1 be2# n14 ad3 b6 v ss e13 v ss l2 be3# p1 ad25 b7 v ss e14 v cc l3 ad28 p2 ad22 b8 v ss f1 v cc l12 ad5 p3 ad19 b9 v ss f2 v ss l13 ad1 p4 ad18 b10 xint6# f3 bstat l14 v cc p5 v cc b11 xint4# f12 rdyrcv# m1 ad30 p6 v cc b12 xint3# f13 v ss m2 ad29 p7 v cc b13 tck f14 v cc m3 nc p8 v cc b14 nc g1 v cc m4 ad23 p9 v cc c1 lock#/once# g2 v ss m5 ad21 p10 v cc c2 holda g3 ale m6 ad17 p11 v cc c3 blast# g12 nc m7 ad16 p12 ad13 c4 a3 g13 v ss m8 ad15 p13 ad11 c5 a2 g14 v cc m9 ad14 p14 ad6 note: do not connect any external logic to pins marked nc (no connect pins).
8 0 960 j a / j f / j d / j s /jc / j t 3 . 3 v e m b e dd e d 32 - b i t m i cr op r o c es s o r da t as h e e t 2 7 3 . 2 . 3 8 0 9 6 0j x 1 32 - l e a d p q fp p i nou t f igu r e 5 . 1 3 2 -l ea d p q f p - t op v i e w 8 d a 7 d a 6 d a 5 d a 4 d a v c c ) o / i ( v s s ) o / i ( 3 d a 2 d a 1 d a 0 d a v c c ) o / i ( v c c ) e r o c ( v s s ) e r o c ( v c c ) e r o c ( v s s ) e r o c ( l l p c c v v c c ) k l c ( c n c n # v c r y d r v s s ) e r o c ( # t e s e r c n t s e t s v c c ) o / i ( i d t v s s ) o / i ( 7 2 d a v c c ) o / i ( v s s ) o / i ( 8 2 d a 9 2 d a 0 3 d a 1 3 d a v c c ) e r o c ( v s s ) e r o c ( v c c ) o / i ( v s s ) o / i ( # 3 e b # 2 e b # 1 e b # 0 e b t a t s b # e c n o / # k c o l v c c ) o / i ( v s s ) o / i ( v c c ) e r o c ( v s s ) e r o c ( e l a a d l o h # n e d # r / t d v c c ) o / i ( v s s ) o / i ( v c c ) e r o c ( v s s ) e r o c ( # r / w # s d a # c / d # t s a l b 6 6 5 6 4 6 3 6 2 6 1 6 0 6 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 5 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 4 9 3 8 3 7 3 6 3 5 3 4 3 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 1 9 0 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 1 0 2 1 1 2 1 2 2 1 3 2 1 4 2 1 5 2 1 6 2 1 7 2 1 8 2 1 9 2 1 0 3 1 1 3 1 2 3 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 t r s t # t c k t m s h o l d x i n t 0 # x i n t 1 # x i n t 2 # x i n t 3 # v c c (i/o ) v s s (i/o ) x i n t 4 # x i n t 5 # x i n t 6 # x i n t 7 # n m i# v c c ( c ore ) v s s ( c ore ) n c n c v c c 5 n c n c f a i l # a l e # t d o v c c (i/o ) v s s (i/o ) wid t h/h l t d 1 v c c ( c ore ) v s s ( c ore ) wid t h/h l t d 0 a 2 a 3 a d 9 v c c (i / o ) a d 1 0 v s s ( i/o ) v c c (i / o ) a d 1 1 v s s ( i/o ) v c c ( c o r e ) v s s ( c ore ) a d 1 2 a d 1 3 a d 1 4 a d 1 5 v c c (i/o ) v s s (i/ o ) ad 1 6 a d 1 7 a d 1 8 a d 1 9 n c v c c (i / o ) a d 2 2 a d 2 5 a d 2 1 a d 2 0 a d 2 4 a d 2 6 a d 2 3 v s s ( i/o ) v c c ( c o r e ) v c c (i / o ) v s s ( c ore ) v s s ( i/o ) v s s ) o / i ( n i k l c v s s ) k l c ( c n v c c ) e r o c ( i xx x x x x x x s s m ? 1 9 x x i96 0 ? x80960jx note: to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 28 datasheet table 13. 132-lead pqfp pinout ? in signal order signal pin signal pin signal pin signal pin ad31 60 ale# 24 v cc (core) 47 v ss (core) 124 ad30 61 ads# 36 v cc (core) 59 v ss (i/o) 10 ad29 62 a3 33 v cc (core) 74 v ss (i/o) 27 ad28 63 a2 32 v cc (core) 92 v ss (i/o) 40 ad27 66 be3# 55 v cc (core) 113 v ss (i/o) 48 ad26 68 be2# 54 v cc (core) 115 v ss (i/o) 56 ad25 69 be1# 53 v cc (core) 123 v ss (i/o) 64 ad24 70 be0# 52 v cc (i/o) 9 v ss (i/o) 71 ad23 75 width/hltd1 28 v cc (i/o) 26 v ss (i/o) 79 ad22 76 width/hltd0 31 v cc (i/o) 41 v ss (i/o) 85 ad21 77 d/c# 35 v cc (i/o) 49 v ss (i/o) 93 ad20 78 w/r# 37 v cc (i/o) 57 v ss (i/o) 97 ad19 81 dt/r# 42 v cc (i/o) 65 v ss (i/o) 106 ad18 82 den# 43 v cc (i/o) 72 v ss (i/o) 112 ad17 83 blast# 34 v cc (i/o) 80 v ss (i/o) 131 ad16 84 rdyrcv# 132 v cc (i/o) 86 nc 18 ad15 87 lock#/once# 50 v cc (i/o) 94 nc 19 ad14 88 hold 4 v cc (i/o) 98 nc 21 ad13 89 holda 44 v cc (i/o) 105 nc 22 ad12 90 bstat 51 v cc (i/o) 111 nc 67 ad11 95 clkin 117 v cc (i/o) 129 nc 121 ad10 96 reset# 125 vccpll 119 nc 122 ad9 99 stest 128 vcc5 20 nc 126 ad8 100 fail# 23 v ss (clk) 118 nc 127 ad7 101 tck 2 v ss (core) 17 xint7# 14 ad6 102 tdi 130 v ss (core) 30 xint6# 13 ad5 103 tdo 25 v ss (core) 38 xint5# 12 ad4 104 trst# 1 v ss (core) 46 xint4# 11 ad3 107 tms 3 v ss (core) 58 xint3# 8 ad2 108 v cc (clk) 120 v ss (core) 73 xint2# 7 ad1 109 v cc (core) 16 v ss (core) 91 xint1# 6 ad0 110 v cc (core) 29 v ss (core) 114 xint0# 5 ale 45 v cc (core) 39 v ss (core) 116 nmi# 15 note: do not connect any external logic to pins marked nc (no connect pins).
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 29 table 14. 132-lead pqfp pinout ? in pin order pin signal pin signal pin signal pin signal 1 trst# 34 blast# 67 nc 100 ad8 2 tck 35 d/c# 68 ad26 101 ad7 3 tms 36 ads# 69 ad25 102 ad6 4 hold 37 w/r# 70 ad24 103 ad5 5 xint0# 38 v ss (core) 71 v ss (i/o) 104 ad4 6 xint1# 39 v cc (core) 72 v cc (i/o) 105 v cc (i/o) 7 xint2# 40 v ss (i/o) 73 v ss (core) 106 v ss (i/o) 8 xint3# 41 v cc (i/o) 74 v cc (core) 107 ad3 9 v cc (i/o) 42 dt/r# 75 ad23 108 ad2 10 v ss (i/o) 43 den# 76 ad22 109 ad1 11 xint4# 44 holda 77 ad21 110 ad0 12 xint5# 45 ale 78 ad20 111 v cc (i/o) 13 xint6# 46 v ss (core) 79 v ss (i/o) 112 v ss (i/o) 14 xint7# 47 v cc (core) 80 v cc (i/o) 113 v cc (core) 15 nmi# 48 v ss (i/o) 81 ad19 114 v ss (core) 16 v cc (core) 49 v cc (i/o) 82 ad18 115 v cc (core) 17 v ss (core) 50 lock#/once# 83 ad17 116 v ss (core) 18 nc 51 bstat 84 ad16 117 clkin 19 nc 52 be0# 85 v ss (i/o) 118 v ss (clk) 20 vcc5 53 be1# 86 v cc (i/o) 119 vccpll 21 nc 54 be2# 87 ad15 120 v cc (clk) 22 nc 55 be3# 88 ad14 121 nc 23 fail# 56 v ss (i/o) 89 ad13 122 nc 24 ale# 57 v cc (i/o) 90 ad12 123 v cc (core) 25 tdo 58 v ss (core) 91 v ss (core) 124 v ss (core) 26 v cc (i/o) 59 v cc (core) 92 v cc (core) 125 reset# 27 v ss (i/o) 60 ad31 93 v ss (i/o) 126 nc 28 width/hltd1 61 ad30 94 v cc (i/o) 127 nc 29 v cc (core) 62 ad29 95 ad11 128 stest 30 v ss (core) 63 ad28 96 ad10 129 v cc (i/o) 31 width/hltd0 64 v ss (i/o) 97 v ss (i/o) 130 tdi 32 a2 65 v cc (i/o) 98 v cc (i/o) 131 v ss (i/o) 33 a3 66 ad27 99 ad9 132 rdyrcv# note: do not connect any external logic to pins marked nc (no connect pins).
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 30 datasheet 3.2.4 80960jx 196-ball mpbga pinout figure 6. 196-ball mini plastic ball grid array top view-balls facing down nc ad8 v cc ad13 ad15 v cc ad18 v cc ad22 v cc nc v cc ad28 nc ad4 ad7 ad9 ad10 ad12 ad14 ad17 ad20 ad23 v cc ad29 ad27 ad30 v cc ad2 ad6 ad11 v cc v cc ad16 ad19 ad21 ad24 ad25 ad26 ad31 nc nc nc nc nc v cc nc nc v cc nc nc v cc nc nc be3# be1# bstat be0# v cc lock#/ ale v cc den# holda ad1 ad0 v cc v cc vccpll v cc v cc nc clkin nc nc v cc nc reset# tdi stest nc rdyrcv# nc ad5 v cc v cc nc xint0# hold a3 ads# nc nc xint2# nc v cc tck trst# tms v cc vcc5 v cc ale# nc dt/r# v cc xint3# xint1# xint5# xint7# nmi# nc nc fail# width1 width0 v cc blast# nc xint4# nc tdo v cc a2 nc nc d/c# w/r# xint6# p n m l k j h g f e d c b a p n m l k j h g f e d c b a 14 13 12 11 10 9 8 7 6 5 4 3 2 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 be2# v cc nc v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss ad3 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss once#
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 31 figure 7. 196-ball mini plastic ball grid array bottom view-balls facing up p n m l k j h g f e d c b a p n m l k j h g f e d c b a 1413121110987654321 1413121110987654321 nc ad8 v cc ad13 ad15 v cc ad18 v cc ad22 v cc nc v cc ad28 nc ad4 ad7 ad9 ad10 ad12 ad14 ad17 ad20 ad23 v cc ad29 ad27 ad30 v cc ad2 ad6 ad11 v cc v cc ad16 ad19 ad21 ad24 ad25 ad26 ad31 nc nc nc nc nc v cc nc nc v cc nc nc v cc nc nc be3# be1# bstat be0# v cc lock#/ ale v cc den# holda ad1 ad0 v cc v cc vccpll v cc v cc nc clkin nc nc v cc nc reset# tdi stest nc rdyrcv# nc ad5 v cc v cc nc xint0# hold a3 ads# nc nc xint2# nc v cc tck trst# tms v cc vcc5 v cc ale# nc dt/r# v cc xint3# xint1# xint5# xint7# nmi# nc nc fail# width1 width0 v cc blast# nc xint4# nc tdo v cc a2 nc nc d/c# w/r# xint6# be2# v cc nc v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss ad3 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss once#
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 32 datasheet table 15. 196-ball mpbga pinout ? in signal order (sheet 1 of 2) signal pin signal pin signal pin signal pin a2 n5 be0# j2 nc m4 v cc j1 a3 m5 be1# h1 nc n3 v cc k3 ad0 d13 be2# h2 nc n4 v cc k13 ad1 d14 be3# h3 nc n8 v cc l3 ad2 c14 blast# p3 nc n10 v cc m2 ad3 d11 bstat j3 nc p1 v cc m6 ad4 b14 clkin g13 nc p8 v cc m9 ad5 d12 den# l2 nc p9 v cc n6 ad6 c13 d/c# n2 nc p14 v cc p4 ad7 b13 dt/r# m1 nmi# p10 v cc p13 ad8 a13 fail# p7 rdyrcv# l14 vccpll f14 ad9 b12 hold n14 reset# j14 v ss d4 ad10 b11 holda l1 stest k14 v ss d5 ad11 c12 lock#/once# k2 tck m14 v ss d6 ad12 b10 nc a1 tdi j12 v ss d7 ad13 a11 nc a4 tdo n7 v ss d8 ad14 b9 nc a14 tms m12 v ss d9 ad15 a10 nc c1 trst# m13 v ss d10 ad16 c9 nc c3 vcc5 m8 v ss e4 ad17 b8 nc d1 v cc a3 v ss e5 ad18 a8 nc d2 v cc a5 v ss e6 ad19 c8 nc d3 v cc a7 v ss e7 ad20 b7 nc e1 v cc a9 v ss e8 ad21 c7 nc e2 v cc a12 v ss e9 ad22 a6 nc f1 v cc b1 v ss e10 ad23 b6 nc f2 v cc b5 v ss e11 ad24 c6 nc g1 v cc c10 v ss f4 ad25 c5 nc g2 v cc c11 v ss f5 ad26 c4 nc g12 v cc e3 v ss f6 ad27 b3 nc g14 v cc e12 v ss f7 ad28 a2 nc h12 v cc e13 v ss f8 ad29 b4 nc h14 v cc e14 v ss f9 ad30 b2 nc j13 v cc f3 v ss f10 ad31 c2 nc k12 v cc f12 v ss f11 ads# p2 nc l12 v cc f13 v ss g4 ale k1 nc l13 v cc g3 v ss g5 ale# m7 nc m3 v cc h13 v ss g6 note: do not connect any external logic to pins marked nc (no connect pins).
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 33 vss g7 v ss h11 v ss k7 v ss l11 vss g8 v ss j4 v ss k8 width0 p5 vss g9 v ss j5 v ss k9 width1 p6 vss g10 v ss j6 v ss k10 w/r# n1 vss g11 v ss j7 v ss k11 xint0# m11 vss h4 v ss j8 v ss l5 xint1# n12 vss h5 v ss j9 v ss l6 xint2# m10 vss h6 v ss j10 v ss l7 xint3# n13 vss h7 v ss j11 v ss l8 xint4# n9 vss h8 v ss k4 v ss l9 xint5# p12 vss h9 v ss k5 v ss l10 xint6# n11 vss h10 v ss k6 v ss l4 xint7# p11 table 16. 196-ball mpbga pinout ? in pin order (sheet 1 of 2) pin signal pin signal pin signal pin signal a1 nc c11 v cc f7 v ss j3 bstat a2 ad28 c12 ad11 f8 v ss j4 v ss a3 v cc c13 ad6 f9 v ss j5 v ss a4 nc c14 ad2 f10 v ss j6 v ss a5 v cc d1 nc f11 v ss j7 v ss a6 ad22 d2 nc f12 v cc j8 v ss a7 v cc d3 nc f13 v cc j9 v ss a8 ad18 d4 v ss f14 vccpll j10 v ss a9 v cc d5 v ss g1 nc j11 v ss a10 ad15 d6 v ss g2 nc j12 tdi a11 ad13 d7 v ss g3 v cc j13 nc a12 v cc d8 v ss g4 v ss j14 reset# a13 ad8 d9 v ss g5 v ss k1 ale a14 nc d10 v ss g6 v ss k2 lock#/once# b1 v cc d11 ad3 g7 v ss k3 v cc b2 ad30 d12 ad5 g8 v ss k4 v ss b3 ad27 d13 ad0 g9 v ss k5 v ss b4 ad29 d14 ad1 g10 v ss k6 v ss b5 v cc e1 nc g11 v ss k7 v ss b6 ad23 e2 nc g12 nc k8 v ss note: do not connect any external logic to pins marked nc (no connect pins). table 15. 196-ball mpbga pinout ? in signal order (sheet 2 of 2) signal pin signal pin signal pin signal pin note: do not connect any external logic to pins marked nc (no connect pins).
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 34 datasheet b7 ad20 e3 v cc g13 clkin k9 v ss b8 ad17 e4 v ss g14 nc k10 v ss b9 ad14 e5 v ss h1 be1# k11 v ss b10 ad12 e6 v ss h2 be2# k12 nc b11 ad10 e7 v ss h3 be3# k13 v cc b12 ad9 e8 v ss h4 v ss k14 stest b13 ad7 e9 v ss h5 v ss l1 holda b14 ad4 e10 v ss h6 v ss l2 den# c1 nc e11 v ss h7 v ss l3 v cc c2 ad31 e12 v cc h8 v ss l4 v ss c3 nc e13 v cc h9 v ss l5 v ss c4 ad26 e14 v cc h10 v ss l6 v ss c5 ad25 f1 nc h11 v ss l7 v ss c6 ad24 f2 nc h12 nc l8 v ss c7 ad21 f3 v cc h13 v cc l9 v ss c8 ad19 f4 v ss h14 nc l10 v ss c9 ad16 f5 v ss j1 v cc l11 v ss c10 v cc f6 v ss j2 be0# l12 nc l13 nc m10 xint2# n7 tdo p4 v cc l14 rdyrcv# m11 xint0# n8 nc p5 width0 m1 dt/r# m12 tms n9 xint4# p6 width1 m2 v cc m13 trst# n10 nc# p7 fail# m3 nc m14 tck n11 xint6# p8 nc m4 nc n1 w/r# n12 xint1# p9 nc m5 a3 n2 d/c# n13 xint3# p10 nmi# m6 v cc n3 nc n14 hold p11 xint7# m7 ale# n4 nc p1 nc p12 xint5# m8 vcc5 n5 a2 p2 ads# p13 v cc m9 v cc n6 v cc p3 blast# p14 nc table 16. 196-ball mpbga pinout ? in pin order (sheet 2 of 2) pin signal pin signal pin signal pin signal note: do not connect any external logic to pins marked nc (no connect pins).
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 35 4.0 electrical specifications 4.1 absolute maximum ratings this document contains information on products in the production phase of development. the specifications within this datasheet are subject to change without prior notice. verify with your local intel sales office or the world wide web to ensure that you have the latest datasheet and device specification update before finalizing a design. warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. table 17 presents the absolute maximum ratings. 4.2 operating conditions warning: operation beyond the ? operating conditions ? is not recommended and extended exposure beyond the ? operating conditions ? may affect device reliability. table 18 presents the operating conditions for the 80960jx 3.3 v processors. table 17. absolute maximum ratings parameter maximum rating storage temperature ? 65 o c to +150 o c case temperature under bias ? 65 o c to +110 o c supply voltage wrt. v ss ? 0.5 v to + 4.6 v voltage on vcc5 wrt. v ss ? 0.5 v to + 6.5 v voltage on other pins wrt. v ss ? 0.5 v to v cc + 0.5 v table 18. 80960jx operating conditions symbol parameter min max units notes v cc supply voltage 3.15 3.45 v vcc5 input protection bias 3.15 5.5 v ( ? ) f clkin input clock frequency 80960jt-100 80960JC-66 80960JC-50 80960js-33 80960js-25 80960jd-66 80960jd-50 80960jd-40 80960jd-33 80960ja/jf-33 80960ja/jf-25 80960ja-16 15 15 15 15 15 12 12 12 12 12 12 12 33.3 33.3 25 33 25 33.3 25 20 16.67 33.3 25 16 mhz t c operating case temperature pga, mpbga, and pqfp extended temp pqfp and mpbga 0 -40 100 100 c ? see section 4.4, ? vcc5 pin requirements (vdiff) ? on page 36 .
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 36 datasheet 4.3 connection recommendations for clean on-chip power distribution, v cc and v ss pins separately feed the device ? s functional units. power and ground connections must be made to all 80960jx power and ground pins. on the circuit board, every v cc pin should connect to a power plane and every v ss pin should connect to a ground plane. place liberal decoupling capacitance near the 80960jx, since the processor may cause transient power surges. the 80960js/jc/jt processors are produced on intel ? s advanced cmos process. proper bulk decoupling must be used to prevent device damage during initial power up and during transitions from low power mode to normal processor operation. power supply behavior during these transitions may cause the power supply to exceed the maximum v cc specification and may cause device damage. pay special attention to the test reset (trst#) pin. it is essential that the jtag boundary scan test access port (tap) controller initializes to a known state whether it may be used or not. when the jtag boundary scan function may be used, connect a pull-down resistor between the trst# pin and v ss . when the jtag boundary scan function may not be used (even for board-level testing), connect the trst# pin to v ss . do not connect the tdi, tdo, and tck pins when the tap controller may not be used. note: pins identified as nc must not be connected in the system. 4.4 vcc5 pin requirements (vdiff) in 3.3 v only systems where the 80960jx input pins are driven from 3.3 v logic, connect the vcc5 pin directly to the 3.3 v v cc plane. in mixed voltage systems where the processor is powered by 3.3 v and interfaces with 5 v components, vcc5 must be connected to 5 v. this allows proper 5 v tolerant buffer operation, and prevents damage to the input pins. the voltage differential between the 80960jx vcc5 pin and its 3.3 v v cc pins must not exceed 2.25 v. when this requirement is not met, current flow through the pin may exceed the value at which the processor is damaged. instances when the voltage may exceed 2.25 v is during power up or power down, where one source reaches its level faster than the other, briefly causing an excess voltage differential. another instance is during steady-state operation, where the differential voltage of the regulator (provided a regulator is used) cannot be maintained within 2.25 v. two methods are possible to prevent this from happening: use a regulator that is designed to prevent the voltage differential from exceeding 2.25 v. or: as shown in figure 8 , place a 100 ? resistor in series with the vcc5 pin to limit the current through vcc5. figure 8. vcc5 current-limiting resistor +5 v (0.25 v) vcc5 pin 100 ?
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 37 when the regulator cannot prevent the 2.25 v differential, the addition of the resistor is a simple and reliable method for limiting current. the resistor may also prevent damage in the case of a power failure, where the 5 v supply remains on and the 3.3 v supply goes to zero. 4.5 vccpll pin requirements to reduce clock skew on the 80960jx processor, the vccpll pin for the phase lock loop (pll) circuit is isolated on the pinout. the lowpass filter, as shown in figure 9 , reduces noise induced clock jitter and its effects on timing relationships in system designs. the 4.7 f capacitor must be low esr solid tantalum; the 0.01 f capacitor must be of the type x7r and the node connecting vccpll must be as short as possible. when the voltage on the vccpll power supply pin exceeds the v cc pin voltage by 0.5 v at any time, including the power up and power down sequences, excessive currents may permanently damage on-chip electrostatic discharge (esd) protection diodes. the damage may accumulate over multiple episodes. in actual applications, this problem occurs only when the vccpll and v cc pins are driven by separate power supplies or voltage regulators. applications that use one power supply for vccpll and v cc are not typically at risk. verify that your application does not allow the vccpll voltage to exceed v cc by 0.5 v. the vccpll low-pass filter recommendation does not promote this problem. table 19. vdiff parameters symbol parameter min max units notes vdiff vcc5-v cc difference 2.25 v vcc5 input should not exceed v cc by more than 2.25 v during power-up and power-down, or during steady- state operation. figure 9. vccpll lowpass filter 100 v cc (board plane) vccpll (on 80960jx) ? ?
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 38 datasheet 4.6 d.c. specifications table 20. 80960jx d.c. characteristics symbol parameter min typ max units notes v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 v cc5 + 0.3 v v ol output low voltage 0.4 v i ol = 3 ma v oh output high voltage 2.4 v i oh = -1 ma v olp output ground bounce <0.8 v ( 1 , 2 ) c in input capacitance pga pqfp mpbga 15 15 15 pf f clkin = f min ( 2 ) c out i/o or output capacitance pga pqfp mpbga 15 15 15 pf f clkin = f min ( 2 ) c clk clkin capacitance pga pqfp mpbga 15 15 15 pf f clkin = f min ( 2 ) notes: 1. typical is measured with v cc = 3.3 v and temperature = 25 c. 2. not tested.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 39 table 21. 80960jx i cc characteristics (sheet 1 of 3) symbol parameter typ max units notes i li1 input leakage current for each pin except tck, tdi, trst# and tms 1 a 0 i li2 input leakage current for tck, tdi, trst# and tms 80960 ja/jf/jd 80960 js/jc/jt -140 -250 -250 -300 a v in = 0.45v ( 1 ) i lo output leakage current 1 a 0.4 r pu internal pull-up resistance for once#, tms, tdi and trst# 20 30 k ? i cc active (power supply) 80960jt-100 80960JC-66 80960JC-50 80960js-33 80960js-25 80960jd-66 80960jd-50 80960jd-40 80960jd-33 80960ja/jf-33 80960ja/jf-25 80960ja-16 505 360 280 240 185 580 447 367 310 320 241 154 ma ( 2 , 3 ) i cc active (thermal) 80960jt-100 80960JC-66 80960JC-50 80960js-33 80960js-25 80960jd-66 80960jd-50 80960jd-40 80960jd-33 80960ja/jf-33 80960ja/jf-25 80960ja-16 480 345 270 221 170 510 390 320 260 271 215 152 ma ( 2 , 4 )
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 40 datasheet i cc te s t (power modes) reset mode 80960jt-100 80960JC-66 80960JC-50 80960js-33 80960js-25 80960jd-66 80960jd-50 80960jd-40 80960jd-33 80960ja/jf-33 80960ja/jf-25 80960ja-16 halt mode 80960jt-100 80960JC-66 80960JC-50 80960js-33 80960js-25 80960jd-66 80960jd-50 80960jd-40 80960jd-33 80960ja/jf-33 80960ja/jf-25 80960ja-16 once mode 380 275 210 240 182 475 425 345 300 250 200 150 52 45 34 35 30 50 40 34 29 31 26 21 10 ma ( 5 ) table 21. 80960jx i cc characteristics (sheet 2 of 3) symbol parameter typ max units notes
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 41 icc5 current on the vcc5 pin 80960jt-100 80960JC-66 80960JC-50 80960js-33 80960js-25 80960jd-66 80960jd-50 80960jd-40 80960jd-33 80960ja/jf-33 80960ja/jf-25 80960ja-16 200 a ( 6 ) notes: 1. these pins have internal pullup devices. typical leakage current is not tested. 2. measured with device operating and outputs loaded to the test condition in figure 10, ? a.c. test load ? on page 45 . 3. i cc active (power supply) value is provided for selecting your system ? s power supply. it is measured using one of the worst case instruction mixes with v cc = 3.45 v. this parameter is characterized but not tested. 4. i cc active (thermal) value is provided for your system ? s thermal management. typical i cc is measured with v cc =3.3 v and temperature = 25 c. this parameter is characterized but not tested. 5. i cc test (power modes) refers to the i cc values that are tested when the 80960jd is in reset mode, halt mode or once mode with v cc = 3.45 v. 6. i cc5 is tested at v cc = 3.3 v, vcc5 = 5.25 v. table 21. 80960jx i cc characteristics (sheet 3 of 3) symbol parameter typ max units notes
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 42 datasheet 4.7 a.c. specifications the 80960jx a.c. timings are based upon device characterization. table 22. 80960jx a.c. characteristics (sheet 1 of 3) symbol parameter min max unit notes input clock timings t f clkin frequency 80960jt-100 80960JC-66 80960JC-50 80960js-33 80960js-25 80960jd-66 80960jd-50 80960jd-40 80960jd-33 80960ja/jf-33 80960ja/jf-25 80960ja-16 15 15 15 15 15 12 12 12 12 12 12 12 33.3 33.3 25 33.3 25 33.3 25 20 16.67 33.3 25 16 mhz t c clkin period 80960jt-100 80960JC-66 80960JC-50 80960js-33 80960js-25 80960jd-66 80960jd-50 80960jd-40 80960jd-33 80960ja/jf-33 80960ja/jf-25 80960ja-16 30 30 40 30 40 30 40 50 60 30 40 62.5 66.7 66.7 66.7 66.7 66.7 83.3 83.3 83.3 83.3 83.3 83.3 83.3 ns t cs clkin period stability 250 ps ( 1 , 2 ) t ch clkin high time 8 ns measured at 1.5 v ( 1 ) t cl clkin low time 8 ns measured at 1.5 v ( 1 ) t cr clkin rise time 4 ns 0.8 v to 2.0 v ( 1 ) t cf clkin fall time 4 ns 2.0 v to 0.8 v ( 1 ) note: see table 23 on page 45 for note definitions for this table.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 43 synchronous output timings t ov1 output valid delay, except ale/ale# inactive and dt/r# for 3.3 v input signals same as above, but for 5.5 v input signals extended temp mpbga and pqfp (js/jc/jt only): output valid delay, except ale/ale# inactive and dt/r# for 3.3 v input signals same as above, but for 5.5 v input signals 2.5 2.5 1.75 1.75 13.5 16.5 13.5 16.5 ns ( 2 , 11 ) t ov2 output valid delay, dt/r# 80960js/jc/jt 80960jd 80960ja/jf 0.5t c + 7 0.5t c + 7 0.5t c + 4 0.5t c + 9 0.5t c + 9 0.5t c + 18 ns t of output float delay 2.5 13.5 ns ( 4 ) synchronous input timings t is1 input setup to clkin ? ad[31:0], nmi#, xint[7:0]# 80960js/jc/jt 80960jd 80960ja/jf 6 6 9 ns ( 5 ) t ih1 input hold from clkin ? ad[31:0], nmi#, xint[7:0]# 80960js/jc/jt 80960jd 80960ja/jf 2.0 1.5 1.0 ns ( 5 ) t is2 input setup to clkin ? rdyrcv# and hold 80960js/jc/jt 80960jd 80960ja/jf 6.5 6.5 10.0 ns ( 6 ) t ih2 input hold from clkin ? rdyrcv# and hold 1ns( 6 ) t is3 input setup to clkin ? reset# 80960js/jc/jt 80960jd 80960ja/jf 7 7 8 ns ( 7 ) t ih3 input hold from clkin ? reset# 80960js/jc/jt 80960jd 80960ja/jf 2 2 1 ns ( 7 ) t is4 input setup to reset# ? once#, stest 80960js/jc/jt 80960jd 80960ja/jf 7 7 8 ns ( 8 ) table 22. 80960jx a.c. characteristics (sheet 2 of 3) symbol parameter min max unit notes note: see table 23 on page 45 for note definitions for this table.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 44 datasheet t ih4 input hold from reset# ? once#, stest 80960js/jc/jt 80960jd 80960ja/jf 2 2 1 ns ( 8 ) relative output timings t lx address valid to ale/ale# inactive for 3.3 v data input signals for 5.0 v data input signals 0.5t c - 5 0.5t c - 8 ns ( 9 ) t lxl ale/ale# width 0.5t c - 7 ns equal loading ( 9 ) t lxa address hold from ale/ale# inactive t dxd dt/r# valid to den# active boundary scan test signal timings t bsf tck frequency 0.5t f mhz t bsch tck high time 15 ns measured at 1.5 v ( 1 ) t bscl tck low time 15 ns measured at 1.5 v ( 1 ) t bscr tck rise time 5 ns 0.8 v to 2.0 v ( 1 ) t bscf tck fall time 5 ns 2.0 v to 0.8 v ( 1 ) t bsis1 input setup to tck ? tdi, tms 4 ns t bsih1 input hold from tck ? tdi, tms 6 ns t bsov1 tdo valid delay 3 30 ns ( 1 , 10 ) t bsof1 tdo float delay 3 30 ns ( 1 , 10 ) t bsov2 all outputs (non-test) valid delay 3 30 ns ( 1 , 10 ) t bsof2 all outputs (non-test) float delay 3 30 ns ( 1 , 10 ) t bsis2 input setup to tck ? all inputs (non-test) 4ns t bsih2 input hold from tck ? all inputs (non-test) 6ns table 22. 80960jx a.c. characteristics (sheet 3 of 3) symbol parameter min max unit notes note: see table 23 on page 45 for note definitions for this table.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 45 4.7.1 a.c. test conditions and derating curves the a.c. specifications in section 4.7, ? a.c. specifications ? are tested with the 50 pf load indicated in figure 10 . refer to the following sections for the specified derating curves: section 4.7.1.1, ? output delay or hold vs. load capacitance ? on page 46 section 4.7.1.2, ? tlx vs. ad bus load capacitance ? on page 47 table 23. note definitions for table 22, 80960jx ac characteristics notes: 1. not tested. 2. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have any power peaking between 500 khz and 1/3 of the clkin frequency. 3. inactive ale/ale# refers to the falling edge of ale and the rising edge of ale#. for inactive ale/ale# timings, refer to relative output timings in this table. 4. a float condition occurs when the output current becomes less than i ol . float delay is not tested, but is designed to be no longer than the valid delay. 5. ad[31:0] are synchronous inputs. setup and hold times must be met for proper processor operation. nmi# and xint[7:0]# may be synchronous or asynchronous. meeting setup and hold time guarantees recognition at a particular clock edge. for asynchronous operation, nmi# and xint[7:0]# must be asserted for a minimum of two clkin periods to ensure recognition. 6. rdyrcv# and hold are synchronous inputs. setup and hold times must be met for proper processor operation. 7. reset# may be synchronous or asynchronous. meeting setup and hold time guarantees recognition at a particular clock edge. 8. once# and stest# must be stable at the rising edge of reset# for proper operation. 9. guaranteed by design. may not be 100% tested. 10.relative to falling edge of tck. 11.worst-case t ov condition occurs on i/o pins when pins transition from a floating high input to driving a low output state. the address/data bus pins encounter this condition between the last access of a read, and the address cycle of a following write. 5 v signals take 3 ns longer to discharge than 3.3 v signals at 50 pf loads. figure 10. a.c. test load output pin c l = 50 pf for all signals c l
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 46 datasheet 4.7.1.1 output delay or hold vs. load capacitance figure 11. output delay or hold vs. load capacitance ? 80960js/jc/jt (3.3 v signals) figure 12. output delay or hold vs. load capacitance ? 80960js/jc/jt (5 v signals) ac timings vs. load capacitance (3.3 v signals) nom + 0 nom + 2 nom + 4 nom + 6 nom + 8 nom + 10 50 100 150 ad bus capacitive load (pf) tov (ns) ac timings vs. load capacitance (5 v signals) nom + 0 nom + 2 nom + 4 nom + 6 nom + 8 nom + 10 nom + 12 nom + 14 nom + 16 50 100 150 ad bus capacitive load (pf) tov (ns)
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 47 4.7.1.2 t lx vs. ad bus load capacitance figure 13. output delay or hold vs. load capacitance ? 80960ja/jf/jd figure 14. t lx vs. ad bus load capacitance ? 80960js/jc/jt (3.3 v signals) ac timings vs. load capacitance nom + 0 nom + 1 nom + 2 nom + 3 nom + 4 nom + 5 nom + 6 nom + 7 nom + 8 50 100 150 ad bus capacitive load (pf) tov (ns) rise and fall times are identical. ac timings vs. load capacitance (3.3 v signals) nom - 0 nom - 2 nom - 4 nom - 6 nom - 8 nom - 10 50 100 150 ad bus capacitive load (pf) tlx (ns)
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 48 datasheet note: the t lx derating curve applies only when an imbalance in the capacitive load occurs between the ad bus and ale. the t lx derating is based on a 50 pf load on ale. the derating applies to ale and ale#. note: the t lx derating curve applies only when an imbalance in the capacitive load occurs between the ad bus and ale. the t lx derating is based on a 50 pf load on ale. the derating applies to ale and ale#. figure 15. t lx vs. ad bus load capacitance ? 80960js/jc/jt (5 v signals) figure 16. t lx vs. ad bus load capacitance ? 80960ja/jf/jd ac timings vs. load capacitance (5 v signals) nom - 0 nom - 5 nom - 10 nom - 15 nom - 20 50 100 150 ad bus capacitive load (pf) tlx (ns) ac timings vs. load capacitance nom - 0 nom - 1 nom - 2 nom - 3 nom - 4 nom - 5 nom - 6 nom - 7 nom - 8 50 100 150 ad bus capacitive load (pf) tlx (ns) rise and fall times are identical.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 49 note: the t lx derating curve applies only when an imbalance in the capacitive load occurs between the ad bus and ale. the t lx derating is based on a 50 pf load on ale. the derating applies to ale and ale#. 4.7.1.3 icc active vs. frequency figure 17. i cc active (power supply) vs. frequency ? 80960ja/jf figure 18. 80960ja/jf i cc active (thermal) vs. frequency icc active (power supply) vs frequency 0 50 100 150 200 250 300 350 12 15 18 21 24 27 30 33 clkin frequency mhz icc active (power supply) (ma) icc active (thermal) vs. frequency 0 50 100 150 200 250 300 12 15 18 21 24 27 30 33 cl kin fr e q u e n cy m hz icc active (thermal) (ma)
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 50 datasheet figure 19. 80960jd i cc active (power supply) vs. frequency figure 20. 80960jd i cc active (thermal) vs. frequency icc active (power supply) vs. frequency 0 100 200 300 400 500 600 12 15 18 21 24 27 30 33 clkin fr e q ue n cy (m hz ) icc active (power supply) (ma) icc active (the rm a l) vs. fre que ncy 0 100 200 300 400 500 600 12 15 18 21 24 27 30 33 c l kin fr e q u e n cy (m hz ) icc active (thermal) (ma)
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 51 figure 21. 80960JC i cc active (power supply) vs. frequency figure 22. 80960JC i cc active (thermal) vs. frequency icc active (power supply) vs frequency 80960 jc 0 50 100 150 200 250 300 350 400 15 18 21 24 27 30 33 cl kin fr e q u e n cy m hz icc active (power supply) (ma) icc active (thermal) vs frequency 80960 jc 0 50 100 150 200 250 300 350 400 15 18 21 24 27 30 33 clkin frequency mhz icc active (thermal) (ma)
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 52 datasheet figure 23. 80960js i cc active (power supply) vs. frequency figure 24. 80960js i cc active (thermal) vs. frequency icc active (power supply) vs frequency 80960 js 0 50 100 150 200 250 300 15 18 21 24 27 30 33 clkin fr e q ue n cy m hz icc active (power supply) (ma) icc active (thermal) vs. frequency 80960 js 0 50 100 150 200 250 15 18 21 24 27 30 33 clkin frequency mhz icc active (thermal) (ma)
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 53 4.7.2 a.c. timing waveforms figure 25. clkin waveform figure 26. t ov1 output delay waveform 2.0 v 1. 5v 0.8 v t cf t ch t cl t c t cr clkin ad[31:0], ale (active), ale# (active), ads#, a[3:2], be[3:0]#, width/hltd[1:0], d/c#, w/r#, den#, blast#, lock#, holda, bstat, fail# 1.5 v 1.5 v 1.5 v t ov1
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 54 datasheet figure 27. t of output float waveform figure 28. t is1 and t ih1 input setup and hold waveform figure 29. t is2 and t ih2 input setup and hold waveform 1.5 v 1.5 v t of clkin ad[31:0], ale, ale# ads#, a[3:2], be[3:0]#, width/hltd[1:0], d/c#, w/r#, dt/r#, den#, blast#, lock# clkin ad[31:0] 1.5 v 1.5 v 1.5 v t is1 t ih1 1.5 v nmi# xint[7:0]# valid clkin valid hold, 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v t is2 t ih2 rdyrcv#
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 55 figure 30. t is3 and t ih3 input setup and hold waveform figure 31. t is4 and t ih4 input setup and hold waveform clkin reset# 1.5 v 1.5 v t ih3 t is3 reset# valid once#, t is4 t ih4 stest
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 56 datasheet figure 32. t lx , t lxl and t lxa relative timings waveform figure 33. dt/r# and den# timings waveform clkin ale 1.5 v 1.5 v 1.5 v ale# 1.5 v 1.5 v ad[31:0] valid t lxa t a t w /t d 1.5 v valid 1.5 v t lxl t lx clkin dt/r# 1.5 v 1.5 v 1.5 v den# valid t dxd t a t w /t d t ov1 t ov2
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 57 figure 34. tck waveform figure 35. t bsis1 and t bsih1 input setup and hold waveforms figure 36. t bsov1 and t bsof1 output delay and output float waveform 2.0 v 1.5 v 0.8 v t bsch t bscl t bscf t bscr tck tms 1.5 v 1.5 v 1.5 v tdi 1.5v 1.5v valid t bsis1 t bsih1 tck 1.5 v 1.5 v 1.5 v t bsov1 tdo valid t bsof1 1.5 v
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 58 datasheet figure 37. t bsov2 and t bsof2 output delay and output float waveform figure 38. t bsis2 and t bsih2 input setup and hold waveform tck 1.5 v 1.5 v 1.5 v t bsov2 non-test valid t bsof2 outputs 1.5 v tck non-test 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v valid t bsis2 t bsih2 inputs
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 59 5.0 device identification 80960jx processors may be identified electrically, according to device type and stepping (see figure 39 , and table 25 through table 30 ). table 24 identifies the device type and stepping for all 5 v, 80960jx processors. figure 39 , and table 25 through table 30 identify all 3.3 v to 5 v-tolerant 80960jx processors. the device id was enhanced to differentiate between 3.3 v and 5 v supply voltages, and between non-clock-doubled and clock-doubled cores when stepping from the a2 stepping to the c0 stepping. the 32-bit identifier is accessible in several ways: upon reset, the identifier is placed into the g0 register. the identifier may be accessed from supervisor mode at any time by reading the deviceid register at address ff008710h. the ieee standard 1149.1 test access port may select the device id register through the idcode instruction. the device and stepping letter is also printed on the top side of the product package. table 24. 80960jx device type and stepping reference device and stepping version number part number manufacturer x complete id (hex) 80960jt a0, a1 0000 0000 1000 0010 1011 0000 0001 001 1 0082b013 80960JC a1 0011 0000 1000 0011 0011 0000 0001 001 1 30833013 80960js a1 0011 0000 1000 0010 0011 0000 0001 001 1 30823013 80960jd c0 0011 0000 1000 0011 0000 0000 0001 001 1 30830013 80960jf c0 0011 0000 1000 0010 0000 0000 0001 001 1 30820013 80960ja c0 0011 0000 1000 0010 0001 0000 0001 001 1 30821013
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 60 datasheet 5.1 80960js/jc/jt device identification register figure 39. 80960js/jc/jt device identification register fields table 25. 80960js/jc/jt device id register field definitions field value definition version see table 26 indicates major stepping changes. v cc 0 = 3.3 v device indicates that a device is 3.3 v. product type 000 100 (indicates i960 cpu) designates type of product. generation type 0001 = j-series indicates the generation (or series) to which the product belongs. model d dpcc d = clock multiplier (01) clock-tripled (p) product derivative (0) jx c = cache size (11) 16k i-cache, 4k d-cache indicates member within a series and specific model information. manufacturer id 000 0000 1001 (indicates intel) manufacturer id assigned by ieee. table 26. 80960js/jc/jt device id model types device version v cc product gen. model manufacturer id ? 1 ? 80960jt a0, a1 0000 0 000100 0001 01011 00000001001 1 80960JC a1 0000 0 000100 0001 10011 00000001001 1 80960js a1 0000 0 000100 0001 00011 00000001001 1 28 24 20 40 16 12 8 1 1 0 0 1 0 0 0 0 0 0 0 manufacturer id part number version model gen product type v cc 1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 61 5.2 80960jd device identification register figure 40. 80960jd device identification register fields table 27. 80960jd device id field definitions field value definition version see table 24 . indicates major stepping changes. v cc 0 = 3.3 v device 1 = 5 v device indicates that a device is 3.3 v. product type 00 0100 (indicates i960 cpu) designates type of product. generation type 0001 = j-series indicates the generation (or series) to which the product belongs. model d000c d = clock doubled (0) not clock-doubled (1) clock doubled c = cache size (0) 4k i-cache, 2k d-cache (1) 2k i-cache, 1k d-cache indicates member within a series and specific model information. manufacturer id 000 0000 1001 (indicates intel) manufacturer id assigned by ieee. table 28. 80960jd device id model types device version v cc product gen. model manufacturer id ? 1 ? 80960jd c0 0011 0 000100 0001 10000 00000001001 1 28 24 20 40 16 12 8 1 1 0 0 1 0 0 0 0 0 0 0 manufacturer id part number version model gen product type v cc 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 62 datasheet 5.3 80960ja/jf device identification register figure 41. 80960ja/jf device identification register fields table 29. 80960ja/jf device id field definitions field value definition version see table 30 . indicates major stepping changes. v cc 0 = 3.3 v device 1 = 5 v device indicates that a device is 3.3 v. product type 00 0100 (indicates i960 cpu) designates type of product. generation type 0001 = j-series indicates the generation (or series) to which the product belongs. model 0000c c = cache size 0 = 4k i-cache, 2k d-cache 1 = 2k i-cache, 1k d-cache indicates member within a series and specific model information. manufacturer id 000 0000 1001 (indicates intel) manufacturer id assigned by ieee. table 30. 80960ja/jf device id model types device version v cc product gen. model manufacturer id ? 1 ? 80960ja c0 0011 0 000100 0001 00001 00000001001 1 80960jf c0 0011 0 000100 0001 00000 00000001001 1 28 24 20 40 16 12 8 1 1 0 0 1 0 0 0 0 0 0 0 manufacturer id part number version model gen product type v cc 1 0 0 0 0 0 1 0 0 0 0 1
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 63 6.0 thermal specifications the 80960jx is specified for operation when t c (case temperature) is within the range of 0 c to 100 c for pga, mpbga and pqfp packages. extended temperature devices are also available in a pqfp package and an mpbga package with t c = -40 c to 100 c. case temperature may be measured in any environment to determine whether the 80960jx is within its specified operating range. the case temperature should be measured at the center of the top surface, opposite the pins. ca is the thermal resistance from case to ambient. use the following equation to calculate t a , the maximum ambient temperature to conform to a particular case temperature: t a = t c - p ( ca ) junction temperature (t j ) is commonly used in reliability calculations. t j may be calculated from jc (thermal resistance from junction to case) using the following equation: t j = t c + p ( jc ) similarly, when t a is known, the corresponding case temperature (t c ) may be calculated as follows: t c = t a + p ( ca ) compute p by multiplying i cc from table 21, ? 80960jx icc characteristics ? on page 39 and v cc . see the following tables for jc and ca values: for high speed operation, the processor ? s ja may be significantly reduced by adding a heatsink and/or by increasing airflow. refer to the following tables for the maximum ambient temperature (t a ) permitted without exceeding t c for the pga, mpbga, and pqfp packages. the values are based on typical i cc and v cc of +3.3 v, with a t c of +100 c. table 31. thermal resistance for and reference table package table pga package table 33 on page 64 mpbga package table 34 on page 64 and table 35 on page 65 pqfp package table 36 on page 65 table 32. maximum ambient temperature reference table processor table 80960jt processor table 37 on page 66 80960JC processor table 38 on page 66 80960jd processor table 39 on page 67 80960js processor table 40 on page 67 80960ja/jf processor table 41 on page 68
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 64 datasheet table 33. 132-lead pga package thermal characteristics thermal resistance ? c/watt parameter airflow ? ft./min (m/sec) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.08) notes: 1. this table applies to a pga device plugged into a socket or soldered directly into a board. 2. table 34. 80960ja/jf/jd 196-ball mpbga package thermal characteristics thermal resistance ? c/watt parameter airflow ? ft./min (m/sec) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.08) notes: 1. this table applies to an mpbga device soldered directly into a board with all v ss connections. 2.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 65 table 35. 80960js/jc/jt 196-ball mpbga package thermal characteristics thermal resistance ? c/watt parameter airflow ? ft./min (m/sec) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.08) notes: 1. this table applies to an mpbga device soldered directly into a board with all v ss connections. 2. table 36. 132-lead pqfp package thermal characteristics thermal resistance ? c/watt parameter airflow ? ft./min (m/sec) 0 (0) 50 (0.25) 100 (0.50) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) notes: 1. this table applies to a pqfp device soldered directly into board. 2.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 66 datasheet table 37. maximum t a at various airflows in c (80960jt) airflow-ft/min (m/sec) f clkin (mhz) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.07) pqfp package t a without heatsink 33 63 74 78 82 86 87 pga package t a without heatsink 33 60 70 78 81 82 84 t a with omnidirectional heatsink 1 33 76 86 90 92 94 94 t a with unidirectional heatsink 2 33 74 87 90 92 94 94 mpbga package t a without heatsink 33 46 60 63 65 66 68 notes: 1. 0.248 inch high omnidirectional heatsink (ai alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing). 2. 0.250 inch high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing). table 38. maximum t a at various airflows in c (80960JC) airflow-ft/min (m/sec) f clkin (mhz) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.07) pqfp package t a without heatsink 33 25 20 16.67 75 79 84 86 82 86 89 90 85 87 90 92 88 90 92 93 90 92 94 95 91 93 94 95 pga package t a without heatsink 33 25 20 16.67 73 78 83 85 79 83 87 89 85 87 90 92 87 89 92 93 88 90 92 93 89 91 93 94 t a with omnidirectional heatsink 1 33 25 20 16.67 84 87 90 91 90 92 94 95 93 95 96 96 95 96 97 97 96 96 97 98 96 96 97 98 t a with unidirectional heatsink 2 33 25 20 16.67 82 86 89 90 91 93 94 95 93 95 96 96 95 96 97 97 96 96 97 98 96 96 97 98 mpbga package t a without heatsink 33 25 20 16.67 63 69 76 80 73 78 83 85 75 79 84 86 76 80 85 87 77 81 85 87 78 82 86 88 notes: 1. 0.248 inch high omnidirectional heatsink (ai alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing). 2. 0.250 inch high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 67 table 39. maximum t a at various airflows in c (80960jd) airflow-ft/min (m/sec) f clkin (mhz) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.07) pqfp package t a without heatsink 33 25 20 16.67 61 70 75 79 73 79 82 86 76 82 85 87 81 86 88 90 85 88 90 92 86 90 91 93 pga package t a without heatsink 33 25 20 16.67 58 68 73 78 68 75 79 83 76 82 85 87 80 84 87 89 81 86 88 90 83 87 89 91 t a with omnidirectional heatsink 1 33 25 20 16.67 75 81 84 87 85 88 90 92 90 92 93 95 92 94 95 96 93 95 96 96 93 95 96 96 t a with unidirectional heatsink 2 33 25 20 16.67 73 79 82 86 86 90 91 93 90 92 93 95 92 94 95 96 93 95 96 96 93 96 96 96 mpbga package t a without heatsink 25 61 72 74 76 77 77 notes: 1. 0.248 inch high omnidirectional heatsink (ai alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing). 2. 0.250 inch high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing). table 40. maximum t a at various airflows in c (80960js) airflow-ft/min (m/sec) f clkin (mhz) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.07) pqfp package t a without heatsink 33 25 16.67 84 86 91 89 90 94 90 92 94 92 93 96 94 95 96 94 95 97 pga package t a without heatsink 33 25 16.67 83 85 90 87 89 92 90 92 94 92 93 95 92 93 96 93 94 96 t a with omnidirectional heatsink 1 33 25 16.67 90 91 94 94 95 96 96 96 98 97 97 98 97 98 98 97 98 98 t a with unidirectional heatsink 2 33 25 16.67 89 90 94 94 95 97 96 96 98 97 97 98 97 98 98 97 98 98 mpbga package t a without heatsink 33 25 16.67 76 80 86 83 85 90 84 86 91 85 87 91 85 87 92 86 88 92 notes: 1. 0.248 inch high omnidirectional heatsink (ai alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing). 2. 0.250 inch high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
80 9 60 j a / j f / j d / j s /jc / j t 3 . 3 v e m b e dd e d 3 2 - b i t m i cr op r o c es s o r 6 8 d a t a s h e e t 6 . 1 t he r m a l m a n age ment ac c essor i e s t h e f o ll o wing is a lis t o f s u g g este d sou r ce s f o r 80 9 60 j x t h e r m a l s o l u ti o n s . t h is i s n e i t h e r a n end o r s e m ent o r a war r anty o f the p e rf o r ma n ce of any o f the l i s ted p r o d uct s and/ o r co m p anie s . 6 . 1 . 1 h e a t s i n k s 1 . thermall o y , inc . 20 2 1 w e s t v a ll e y v i e w lan e d a ll a s , t x 7 52 3 4- 8 99 3 (9 7 2) 2 43 - 43 2 1 2 . w a kef i e l d e ng i n e er ing 6 0 a u d u b o n ro a d w a kef i e ld, m a 01 8 8 0 (6 1 7 ) 2 4 5 - 59 0 0 3 . a a v id t h ermal t ech n o lo g i e s , inc . o n e k o o l p a th lacon ia, n h 03 2 47 - 04 0 0 (6 0 3 ) 5 2 8 - 34 0 0 t a b le 4 1 . m ax i m u m t a a t v ar iou s a i r f l o w s i n c ( 8 0 960 j a/j f ) a i rf low - f t / m i n (m / sec ) f c l k i n (mh z ) 0 (0 ) 20 0 ( 1 . 01 ) 40 0 ( 2 . 03 ) 60 0 ( 3 . 04 ) 80 0 ( 4 . 06 ) 100 0 ( 5 . 07 ) pqf p p acka g e f o r x80960j a / j f t a wi t hou t hea t s in k 3 3 2 5 1 6 7 9 8 4 8 9 8 6 8 9 9 2 8 7 9 0 9 3 9 0 9 2 9 5 9 2 9 4 9 6 9 3 9 4 9 6 f o r x 809 6 0ja- 2 5 t a wi t hou t hea t s in k 2 5 8 4 8 9 9 0 9 2 9 4 9 4 p g a p acka g e t a wi t hou t hea t s in k 3 3 2 5 1 6 7 8 8 3 8 8 8 3 8 7 9 1 8 7 9 0 9 3 8 9 9 2 9 4 9 0 9 2 9 5 9 1 9 3 9 5 t a wi t h o m n i di r e c t ional hea t sin k 1 3 3 2 5 1 6 8 7 9 0 9 3 9 2 9 4 9 6 9 5 9 6 9 7 9 6 9 7 9 8 9 6 9 7 9 8 9 6 9 7 9 8 t a wi t h unidirec t i onal hea t sin k 2 3 3 2 5 1 6 8 6 8 9 9 2 9 3 9 4 9 6 9 5 9 6 9 7 9 6 9 7 9 8 9 6 9 7 9 8 9 6 9 7 9 8 m p b g a p acka g e t a wi t hou t hea t s in k 3 3 2 5 7 3 7 9 8 0 8 4 8 2 8 6 8 3 8 7 8 4 8 7 8 4 8 7 not e s : 1 . 0 . 248 i n c h high omnidirec t ional hea t sink ( a i al l o y 6061 , 4 1 m i l f i n w i d t h , 124 mil c en t e r - t o - cen t er f i n s p acing) . 2 . 0 . 250 i n c h high unid i r ec t i onal hea t s i nk ( a i alloy 6061 , 50 mil f i n wi d t h , 146 m i l cen t er- t o-ce n t er f i n s p acing) . 3. to address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x".
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 69 7.0 bus functional waveforms figure 42 through figure 47 illustrate typical 80960jx bus transactions. figure 48 depicts the bus arbitration sequence. figure 49 illustrates the processor reset sequence from the time power is applied to the device. figure 50 illustrates the processor reset sequence when the processor is in operation. figure 51 illustrates the processor once# sequence from the time power is applied to the device. figure 53 and figure 54 also show accesses on 32-bit buses. table 44 through table 46 summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to data alignment. figure 42. non-burst read and write transactions without wait states, 32-bit bus clkin ad31:0 ale ads# a3:2 be3:0# width1:0 d/c# w/r# dt/r# den# rdyrcv# blast# addr d in invalid addr data out 10 10 t a t d t r t i t i t a t d t r t i t i f_jf030a
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 70 datasheet figure 43. burst read and write transactions without wait states, 32-bit bus addr d d addr data data data data 1 0 1 0 clkin ad31:0 ale ads# a3:2 be3:0# width1:0 d/c# w/r# blast# dt/r# den# rdyrcv# t a t d t d t r t a t d t d t d t d t r in in out out out out 00 or 10 01 or 11 00 01 10 11
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 71 figure 44. burst write transactions with 2,1,1,1 wait states, 32-bit bus addr data 1 0 data data data clkin ad31:0 ale ads# a3:2 be3:0# width1:0 d/c# w/r# blast# dt/r# den# rdyrcv# t a t w t w t d t w t d t w t d t w t d t r out out out out f_jf032a 0 0 0 1 1 0 1 1
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 72 datasheet figure 45. burst read and write transactions without wait states, 8-bit bus addr d d addr data data data data clkin ad31:0 ale ads# a3:2 be1#/a1 width1:0 d/c# w/r# blast# dt/r# den# rdyrcv# t a t d t d t r t a t d t d t d t d t r 00,01,10 or 11 00,01,10 or 11 00 01 10 11 00 00 be0#/a0 in in out out out out f_jf033a 00 or 10 01 or 11
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 73 figure 46. burst read and write transactions with 1, 0 wait states and extra tr state on read, 16-bit bus addr d d addr data data clkin ad31:0 ale ads# a3:2 be3#/bhe width1:0 d/c# w/r# blast# dt/r# den# rdyrcv# t w t d t d t r t r t a t w t d t d t r 00,01,10, or 11 00,01,10, or 11 t a be0#/ble be1#/a1 01 01 0 1 01 out out in in f_jf034a
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 74 datasheet figure 47. double word read bus request, misaligned one byte from quad word boundary, 32-bit bus, little endian t a t d t r t a t d t r t a t d t r t a t d t r clkin ad31:0 ale ads# a3:2 be3:0# width1:0 d/c# w/r# blast# dt/r# den# rdyrcv# 00 00 01 10 1 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 valid aa a d a d in in d in d in
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 75 figure 48. hold/holda waveform for bus arbitration clkin valid outputs: ad31:0, ale, ale#, ads#, a3:2, be3:0#, width/hltd1:0, d/c#, w/r#, dt/r#, den#, blast#, lock# hold holda ~ ~ ~ ~ ~ ~ ~ ~ (note) note: hold is sampled on the rising edge of clkin. the processor asserts holda to grant the bus on the same edge in which it recognizes hold when the last state was t i or the last t r of a bus transaction. similarly, valid ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t i or t r t h t h t i or t a the processor deasserts holda on the same edge in which it recognizes the deassertion of hold.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 76 datasheet figure 49. cold reset waveform clkin ale#, ads#, ale#,w/r#, reset# lock#/ stest v cc dt/r# fail# ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ first bus activity ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ valid ~ ~ (output) once# ad31:0, a3:2,d/c# ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ (note 1) ~ ~ ~ ~ idle (note 2) hold ~ ~ valid input (note 3) ~ ~ ~ ~ ~ ~ ~ ~ be3:0#, den#, blast# ~ ~ ~ ~ ~ ~ valid output (note 3) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ holda v 10,000 clkin periods, for pll stabilization. cc and clkin stable to reset high, minimum ~ ~ built-in self-test (note 4) (input) ~ ~ 1. the processor asserts fail# during built-in self-test. when self- test passes, the fail# pin is deasserted.the processor als o asserts fail# during the bus confidence test. when the bus confidence test passes, fail# is deasserted and the processor begins user program execution. notes: 2. if the processor fails built-in self-test, it initiates one dummy load bus access. the load address indicates the point of s elf-test failure. 3. since the bus is idle, hold requests are honored during reset and built-in self-test. ~ ~ ~ ~ width/hltd1:0 4. when selected, built-in self test requires approximately (in clkin periods): 393,000 for 80960jt, 580,012 for the 80960JC, ~ ~ 1,176,025 for the 80960js, 207,000 for 80960jd, and 414,000 for 80960ja/jf.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 77 figure 50. warm reset waveform ~ ~ ~ ~ maximum reset# low to reset state 4 clkin cycles ~ ~ ~ ~ ~ ~ clkin ad31:0, a3:2, d/c# stest reset# ~ ~ ~ ~ reset# high to first bus minimum reset# low time 15 clkin cycles ~ ~ ~ ~ ~ ~ ~ ~ holda ~ ~ ~ ~ ~ ~ ~ ~ valid ale#, ads#, b e3:0#, den#, blast# ale, w/r#,dt/r#, bstat, width/hltd1:0 ~ ~ ~ ~ fail# ~ ~ ~ ~ ~ ~ hold ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ lock#/once# ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ activity: (clkin cycles) ~ ~ ~ ~ ~ ~ ~ ~ 80960jd - 46 80960ja/jf - 92 80960jt - 26 80960js - 60 80960JC - 40
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 78 datasheet figure 51. entering the once state clkin ale#, ads#, ale,w/r,# reset# lock#/ v cc dt/r#, width/hltd1:0 fail# ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ once# ad31:0, a3:2, d/c# ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ hold ~ ~ ~ ~ ~ ~ be3:0#, den#, blast# ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ holda ~ ~ ~ ~ (input) minimum 10,000 clkin periods, for pll v cc and clkin stable to reset# high, ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ (note 1) 1. once# mode may be entered prior to the rising edge of reset#: once# input is not latched until the rising edge of reset#. notes: clkin may not be allowed to float. ~ ~ ~ ~ stest ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 2. the once# input may be removed after the processor enters once# mode. ~ ~ stabilization. it must be driven high or low or continue to run.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 79 7.1 basic bus states the bus has five basic bus states: idle (ti), address (ta), wait/data (tw/td), recovery (tr), and hold (th). during system operation, the processor continuously enters and exits different bus states. figure 52 shows the five bus states. the bus occupies the idle (ti) state when no address/data transactions are in progress and when reset# is asserted. when the processor needs to initiate a bus access, it enters the ta state to transmit the address. following a ta state, the bus enters the tw/td state to transmit or receive data on the address/data lines. assertion of the rdyrcv# input signal indicates completion of each transfer. when data is not ready, the processor may wait as long as necessary for the memory or i/o device to respond. after the data transfer, the bus exits the tw/td state and enters the recovery (tr) state. in the case of a burst transaction, the bus exits the td state and re-enters the td/tw state to transfer the next data word. the processor asserts the blast# signal during the last tw/td states of an access. once all data words transfer in a burst access (up to four), the bus enters the tr state to allow devices on the bus to recover. the processor remains in the tr state until rdyrcv# is deasserted. when the recovery state completes, the bus enters the ti state when no new accesses are required. when an access is pending, the bus enters the ta state to transmit the new address.
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 80 datasheet 7.2 boundary-scan register the boundary-scan register contains a cell for each pin as well as cells for control of i/o and highz pins. table 42 shows the bit order of the 80960jx processor boundary-scan register. all table cells that contain ? ctl ? select the direction of bidirectional pins or highz output pins. when a 1 is loaded into the control cell, the associated pin(s) are highz or selected as input. figure 52. bus states with arbitration ti ? idle state ta ? address state tw / td ? wait/data state tr ? recovery state th ? hold state to ? once state ready ? rdyrcv# asserted not ready ? rdyrcv# not asserted burst ? blast# not asserted no burst ? blast# asserted recovered ? rdyrcv# not asserted not recovered ? rdyrcv# asserted request pending ? new transaction no request ? no new transaction hold ? hold request asserted no hold ? hold request not asserted locked ? atomic execution (atadd, atmod) in progress not locked ? no atomic execution in progress reset ? reset# asserted once ? once# asserted tw/td tr th ti ta hold and not locked hold recovered and no request and (no hold or locked) recovered and request pending and (no hold or locked) no request and no hold to reset not recovered recovered and hold and not locked ready and no burst (ready and burst) or not ready request pending and (no hold or locked) no request and (no hold or locked) once & reset deassertion request pending and no hold
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 81 table 42. boundary-scan register ? bit order bit signal input/ output bit signal input/ output bit signal input/ output 0 rdyrcv# (tdi) i24 den# o48 ad17 i/o 1 hold i25 holda o49 ad16 i/o 2 xint0# i26 ale o50 ad15 i/o 3 xint1# i27 lock#/ once# cell enable cell ? 51 ad14 i/o 4 xint2# i28 lock#/ once# i/o 52 ad13 i/o 5 xint3# i29 bstat o53 ad12 i/o 6 xint4# i30 be0# o54 ad cells enable cell ? 7 xint5# i31 be1# o55 ad11 i/o 8 xint6# i32 be2# o56 ad10 i/o 9 xint7# i33 be3# o57 ad9 i/o 10 nmi# i34 ad31 i/o 58 ad8 i/o 11 fail# i35 ad30 i/o 59 ad7 i/o 12 ale# o36 ad29 i/o 60 ad6 i/o 13 width/hltd1 o37 ad28 i/o 61 ad5 i/o 14 width/hltd0 o38 ad27 i/o 62 ad4 i/o 15 a2 o39 ad26 i/o 63 ad3 i/o 16 a3 o40 ad25 i/o 64 ad2 i/o 17 control1 enable cell ? 41 ad24 i/o 65 ad1 i/o 18 control2 enable cell ? 42 ad23 i/o 66 ad0 i/o 19 blast# o43 ad22 i/o 67 clkin i 20 d/c# o44 ad21 i/o 68 reset# i 21 ads# o45 ad20 i/o 69 stest (tdo) i 22 w/r# o46 ad19 i/o 23 dt/r# o47 ad18 i/o ? enable cells are active low. table 43. natural boundaries for load and store accesses data width natural boundary (bytes) byte 1 short word 2 word 4 double word 8 triple word 16 quad word 16
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 82 datasheet table 44. summary of byte load and store accesses address offset from natural boundary (in bytes) accesses on 8-bit bus (width1:0=00) accesses on 16 bit bus (width1:0=01) accesses on 32 bit bus (width1:0=10) +0 (aligned) byte access byte access byte access table 45. summary of short word load and store accesses address offset from natural boundary (in bytes) accesses on 8-bit bus (width1:0=00) accesses on 16 bit bus (width1:0=01) accesses on 32 bit bus (width1:0=10) +0 (aligned) burst of 2 bytes short-word access short-word access +1 two byte accesses two byte accesses two byte accesses
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 83 table 46. summary of n -word load and store accesses ( n = 1, 2, 3, 4) address offset from natural boundary in bytes accesses on 8-bit bus (width1:0=00) accesses on 16 bit bus (width1:0=01) accesses on 32 bit bus (width1:0=10) +0 (aligned) ( n =1, 2, 3, 4) n burst(s) of 4 bytes case n =1: burst of 2 short words case n =2: burst of 4 short words case n =3: burst of 4 short words burst of 2 short words case n =4: 2 bursts of 4 short words burst of n word(s) +1 ( n =1, 2, 3, 4) +5 ( n = 2, 3, 4) +9 ( n = 3, 4) +13 ( n = 3, 4) byte access burst of 2 bytes n -1 burst(s) of 4 bytes byte access byte access short-word access n -1 burst(s) of 2 short words byte access byte access short-word access n -1 word access(es) byte access +2 ( n =1, 2, 3, 4) +6 ( n = 2, 3, 4) +10 ( n = 3, 4) +14 ( n = 3, 4) burst of 2 bytes n -1 burst(s) of 4 bytes burst of 2 bytes short-word access n -1 burst(s) of 2 short words short-word access short-word access n -1 word access(es) short-word access +3 ( n =1, 2, 3, 4) +7 ( n = 2, 3, 4) +11 ( n = 3, 4) +15 ( n = 3, 4) byte access n -1 burst(s) of 4 bytes burst of 2 bytes byte access byte access n -1 burst(s) of 2 short words short-word access byte access byte access n -1 word access(es) short-word access byte access +4 ( n = 2, 3, 4) +8 ( n = 3, 4) +12 ( n = 3, 4) n burst(s) of 4 bytes n burst(s) of 2 short words n word access(es)
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor 84 datasheet figure 53. summary of aligned and unaligned accesses (32-bit bus) 04 812162024 01 234 5 6 one double-word short-word load/store word load/store double-word load/store byte, byte accesses short access (aligned) short access (aligned) byte, byte accesses word access (aligned) byte, short, byte, accesses short, short accesses byte, short, byte accesses byte offset word offset one double-word burst (aligned) byte, short, word, byte accesses short, word, short accesses byte, word, short, byte accesses word, word accesses burst (aligned)
80960ja/jf/jd/js/jc/jt 3.3 v embedded 32-bit microprocessor datasheet 85 figure 54. summary of aligned and unaligned accesses (32-bit bus) (continued) 04 8 12162024 0 123456 triple-word load/store quad-word load/store word, word, word accesses word, accesses word, word, word, word, word, word, word accesses byte offset word offset one three-word burst (aligned) byte, short, word, word, byte accesses short accesses short, word, word, byte, word, word, short, byte accesses word, word, word accesses one four-word burst (aligned) byte, short, word, word, word, byte accesses short, word, word, word, short accesses byte, word, word, word, short, byte accesses accesses word, word word,
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